0.75V micro-power SI memory cell with feedthrough error reduction

Electronics Letters

Volumn 44, Issue 9, 2008, Pages 561-562

  Sawigun, C ^a   Serdijn, W A ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ERROR ANALYSIS; SWITCHING CIRCUITS; TRANSISTORS;

CLOCK-FEEDTHOUGH (CFT) ERROR REDUCTION; LOW SUPPLY VOLTAGE; MEMORY TRANSISTOR;

POWER ELECTRONICS;

EID: 42449150350     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20080722     Document Type: Article

References (6)

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2. Fiez, T.S., Allstot, D.J., Liang, G., and Lao, P.: ' Signal-dependent clock-feedthrough cancellation in switched current circuits ', Proc. IEEE ISCAS, Singapore, 1991, p. 785-788
3. Toumazou, C., and Xiao, S.: ' An n-step charge injection cancellation scheme for switched current circuits ', Electron. Lett., 1994, 30, p. 680-681 10.1049/el:19940486 0013-5194
4. Helfenstein, M., and Moschytz, G.S.: ' Improved two-step clock-feedthrough compensation technique for switched current circuits ', IEEE Trans. Circuits Syst. II, 1998, 45, (6), p. 739-743 10.1109/82.686693 1057-7130
5. Min, B.M., and Kim, S.W.: ' New clock-feedthrough compensation scheme for switched current circuits ', IEEE Trans. Circuits Syst. II, 1998, 45, (11), p. 1508-1511 10.1109/82.735364 1057-7130
6. Cavajal, R.G., Ramirez-Angulo, J., Lopez-Martin, A.J., Torralba, A., Gomez Galen, J.A., Carlosena, A., and Chavero, F.M.: ' The flipped voltage follower: a useful cell for low-voltage low-power circuit design ', IEEE Trans. Circuits Syst. I, 2005, 52, (7), p. 1276-1291 1057-7122