메뉴 건너뛰기




Volumn , Issue , 2007, Pages 341-344

A Sample-Time Error Compensation Technique for Time-Interleaved ADC Systems

Author keywords

[No Author keywords available]

Indexed keywords

DATA COMMUNICATION SYSTEMS; DIGITAL SIGNAL PROCESSING; ERROR COMPENSATION; ERROR CORRECTION; ERRORS; INTEGRATED CIRCUITS; SIGNAL TO NOISE RATIO;

EID: 42149176141     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405748     Document Type: Conference Paper
Times cited : (6)

References (9)
  • 1
    • 0019265826 scopus 로고
    • Time interleaved converter arrays
    • Dec.
    • W. Black, and D. Hodges, "Time interleaved converter arrays, " IEEE J. Solid-State Circuits, vol. SC-15, pp. 1022-1029, Dec. 1980.
    • (1980) IEEE J. Solid-State Circuits , vol.SC-15 , pp. 1022-1029
    • Black, W.1    Hodges, D.2
  • 2
    • 0026240449 scopus 로고
    • Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer
    • Oct.
    • A. Petraglia, and S. K. Mitra, "Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer, " IEEE Trans. Instrum. Measur., vol. 40, pp. 831-835, Oct. 1991.
    • (1991) IEEE Trans. Instrum. Measur. , vol.40 , pp. 831-835
    • Petraglia, A.1    Mitra, S.K.2
  • 3
    • 0032313025 scopus 로고    scopus 로고
    • A digital background Calibration technique for time-interleaved analog-to-digital converters
    • Dec.
    • D. Fu, K. C. Dyer, S. H. Lewis, and P. J. Hurst, "A digital background Calibration technique for time-interleaved analog-to-digital converters, " IEEE J. Solid-State Circuits, vol. 33, pp. 1904-1911, Dec. 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.33 , pp. 1904-1911
    • Fu, D.1    Dyer, K.C.2    Lewis, S.H.3    Hurst, P.J.4
  • 4
    • 11144254605 scopus 로고    scopus 로고
    • Time-interleaved analog-to-digital converters for digital communications
    • Nov.
    • T. H. Tsai, P. J. Hurst, and S. H. Lewis, "Time-interleaved analog-to-digital converters for digital communications, " Int. Conf. on Circuits, Signals, and Systems, pp. 193-198, Nov. 2004.
    • (2004) T. Conf. On Circuits, Signals, and Systems , pp. 193-198
    • Tsai, T.H.1    Hurst, P.J.2    Lewis, S.H.3
  • 5
    • 0036912842 scopus 로고    scopus 로고
    • A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration
    • Dec.
    • S. M. Jamal, D. Fu, N. C.-J. Chang, P. J. Hurst, and S. H. Lewis, "A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration, " IEEE J. Solid-State Circuits, vol. 37, pp. 1618-1627, Dec. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , pp. 1618-1627
    • Jamal, S.M.1    Fu, D.2    Chang, N.C.-J.3    Hurst, P.J.4    Lewis, S.H.5
  • 8
    • 0034225769 scopus 로고    scopus 로고
    • A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADC's
    • Jul.
    • H. Jin, and E. K. F. Lee, "A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADC's, " IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, pp. 603-613, Jul. 2000.
    • (2000) IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing , vol.47 , pp. 603-613
    • Jin, H.1    Lee, E.K.F.2
  • 9
    • 39549091207 scopus 로고    scopus 로고
    • A background compensation technique for sample-time error in time-interleaved A/D converters
    • May.
    • A. Haftbaradaran, and K. W. Martin, "A background compensation technique for sample-time error in time-interleaved A/D converters, " IEEE Int. Symp. on Circuits and Systems, May. 2006.
    • (2006) IEEE Int. Symp. on Circuits and Systems
    • Haftbaradaran, A.1    Martin, K.W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.