Low voltage operating flash memory cell with high coupling ratio using horned floating gate with fine HSG

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1998, Pages 104-105

  Kitamura, Takuya ^a   Kawata, Masato ^a   Honma, Ichiro ^a   Yamamoto, Ichiro ^a   Nishimoto, Shozo ^a   Oyama, Ken ichi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; INTEGRATED CIRCUIT LAYOUT;

FLASH MEMORY; FLOATING GATE; HEMISPHERICAL GRAINED (HSG) TECHNIQUE;

DATA STORAGE EQUIPMENT;

EID: 0031635770     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)