Simplified max-log-MAP decoder structure

SympoTIC'06 - Joint 1st Workshop on Sensor Networks and Symposium on Trends in Communications

Volumn , Issue , 2006, Pages 10-13

  Salmela, Perttu ^a   Järvinen, Tuomas ^b   Takala, Jarmo ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; MULTIPLEXING; TURBO CODES;

COMPONENT DECODERS; TURBO DECODERS;

DECODING;

EID: 41649083749     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/tic.2006.1708009     Document Type: Conference Paper

References (7)

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2. 3GPP TS 25.212; Multiplexing and Channel coding (FDD), 3rd Generation Partnership Project Std. 4.3.0, Dec. 2001.
3. J. Nikolic-Popovic, Implementing a MAP Decoder for cdma2000 Turbo Codes on a TMS320C62x DSP Device, Texas Instruments, May. 2000, SPRA629.
4. E. Yeo, P. Pakzad, B. Nikolić, and V. Anantharam, "VLSI architectures for iterative decoders in magnetic recording channels," IEEE Trans. Magn., vol. 37, no. 2, pp. 748-755, 2001.
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7. A. J. Viterbi, "An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes," IEEE J. Select. Areas Commun., vol. 16, no. 2, pp. 260-264, Feb. 1998.