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Volumn , Issue , 2005, Pages 173-178

High speed max-log-MAP turbo SISO decoder implementation using branch metric normalization

Author keywords

[No Author keywords available]

Indexed keywords

CELL LIBRARY; DECODER; SOFT-IN-SOFT-OUT (SISO); TURBO DECODER;

EID: 26844562528     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (15)

References (13)
  • 1
    • 0027297425 scopus 로고
    • Near Shannon limit error correction coding and decoding: Turbo codes
    • May
    • C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error correction coding and decoding: Turbo codes", Proc. 1993 Inter. Conf. Commun., May 1993, pp. 1064-1070.
    • (1993) Proc. 1993 Inter. Conf. Commun. , pp. 1064-1070
    • Berrou, C.1    Glavieux, A.2    Thitimajshima, P.3
  • 4
    • 0029234412 scopus 로고
    • A comparison of optimal and sub-optimal decoding algorithm
    • Robertson, E. Villebrun, and P. Hoeher, "A comparison of optimal and sub-optimal decoding algorithm", Proc. IEEE Int. Conf. Commun., 1995, pp. 1009-1013.
    • (1995) Proc. IEEE Int. Conf. Commun. , pp. 1009-1013
    • Robertson, E.V.1    Hoeher, P.2
  • 5
    • 0029516480 scopus 로고
    • Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding
    • Sept.
    • H. Dawid, and H. Meyer, "Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding", IEEE Int. Sym. PIMRC, Vol. 1, Sept. 1995, pp. 193-197.
    • (1995) IEEE Int. Sym. PIMRC , vol.1 , pp. 193-197
    • Dawid, H.1    Meyer, H.2
  • 7
    • 0036625313 scopus 로고    scopus 로고
    • Architecture strategies for low-power VLSI turbo decoders
    • June
    • Masera, M. Mazza, G. Piccinini, F. Viglione, and M. Zamboni, "Architecture Strategies for Low-Power VLSI Turbo Decoders", IEEE Tran. on VLSI Sys. Vol. 10, No. 3, June 2002, pp. 279-285.
    • (2002) IEEE Tran. on VLSI Sys. , vol.10 , Issue.3 , pp. 279-285
    • Masera, M.M.1    Piccinini, G.2    Viglione, F.3    Zamboni, M.4
  • 9
    • 1542329201 scopus 로고    scopus 로고
    • A Low-power VLSI architecture for turbo decoding
    • August
    • S. J. Lee, N. R. Shanbhag, and A. C. Singer, "A Low-Power VLSI Architecture for Turbo Decoding", ISLPED03, August 2003, pp.366-371.
    • (2003) ISLPED03 , pp. 366-371
    • Lee, S.J.1    Shanbhag, N.R.2    Singer, A.C.3
  • 11
    • 0035332876 scopus 로고    scopus 로고
    • Design of fixed-point iterative decoders for concatenated codes with interleavers
    • May
    • G. Montorsi, and S. Benedetto, "Design of Fixed-Point Iterative Decoders for Concatenated Codes with Interleavers", IEEE J. on Selected Areas in Commun. Vol. 19, No. 5, May 2001, pp.871-882.
    • (2001) IEEE J. on Selected Areas in Commun. , vol.19 , Issue.5 , pp. 871-882
    • Montorsi, G.1    Benedetto, S.2
  • 13
    • 0030110651 scopus 로고    scopus 로고
    • Iterative decoding of binary block and convolutional codes
    • March
    • J. Hagenauer, E. Offer, and L. Papke, "Iterative Decoding of Binary Block and Convolutional Codes", IEEE Tran. Info. Theory, Vol. 42, March 1996, pp. 429-445
    • (1996) IEEE Tran. Info. Theory , vol.42 , pp. 429-445
    • Hagenauer, J.1    Offer, E.2    Papke, L.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.