Cache-only memory architectures

Computer

Volumn 32, Issue 6, 1999, Pages 72-79

  Dahlgren, Fredrik ^a   Torrellas, Josep ^b  

^a ERICSSON RESEARCH   (Sweden)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; DATA ACQUISITION; DATA STRUCTURES; DATA TRANSFER; DYNAMIC RANDOM ACCESS STORAGE; NETWORK PROTOCOLS;

ATTRACTION MEMORY; CACHE ONLY MEMORY ARCHITECTURE; LATENCY TOLERATING TECHNIQUES; NONUNIFORM MEMORY ACCESS; REMOTE CACHE;

BUFFER STORAGE;

EID: 0032668949     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.769448     Document Type: Article

References (12)

1. E. Hagersten, A. Landin, and S. Haridi, "DDM - A Cache-Only Memory Architecture," Computer, Sept. 1992, pp. 44-54.
2. P. Stenstrom, T. Joe, and A. Gupta, "Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures," Proc. 19th Int'l Symp. Computer Architecture, IEEE CS Press, Los Alamitos, Calif., 1992, pp. 80-91.
3. T. Joe and J. Hennessy, "Evaluating the Memory Overhead Required for COMA Architectures," Proc. 21st Int'l Symp. Computer Architecture, IEEE CS Press, Los Alamitos, Calif., 1994, pp. 82-93.
4. A. Saulsbury et al., "An Argument for Simple COMA," Proc. 1st Symp. High-Performance Computer Architecture, IEEE CS Press, Los Alamitos, Calif., 1995, pp. 276-285.
5. S. Basu and J. Torrellas, "Enhancing Memory Use in Simple COMA: Multiplexed Simple COMA," Proc. 4th Int'l Symp. High-Performance Computer Architecture, IEEE CS Press, Los Alamitos, Calif., 1998, pp. 152-161.
6. Z. Zhang and J. Torrellas, "Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA," Proc. 3rd Int'l Symp. High-Performance Computer Architecture, IEEE CS Press, Los Alamitos, Calif., 1997, pp. 272-281.
7. B. Verghese et al., "Operating System Support for Improving Data Locality on CC-NUMA Computer Servers," Proc. 7th Int'l Conf. Architectural Support for Programming Languages and Operating Systems, ACM Press, New York, 1996, pp. 279-289.
8. V. Soundararajan et al., "Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM Multi-processors," Proc. 25th Int'l Symp. Computer Architecture, IEEE CS Press, Los Alamitos, Calif., 1998, pp. 342-355.
9. B. Falsafi and D. Wood, "Reactive NUMA: A Design for Unifying S-COMA and CC-NUMA," Proc. 24th Ann. Int'l Symp. Computer Architecture, ACM Press, New York, 1997, pp. 229-239.
10. E. Hagersten and M. Koster, "WildFire: A Scalable Path for SMPs," Proc. 5th Int'l Symp. High-Performance Computer Architecture, IEEE CS Press, Los Alamitos, Calif., 1999, pp. 172-181.
11. K. Ekanadham et al., "PRISM: An Integrated Architecture for Scalable Shared Memory," Proc. 4th Int'l Symp. High-Performance Computer Architecture, IEEE CS Press, Los Alamitos, Calif., 1998, pp. 140-151.
12. A. Moga and M. Dubois, "The Effectiveness of SRAM Network Caches in Clustered DSMs," Proc. 4th Int'l Symp. High-Performance Computer Architecture, IEEE CS Press, Los Alamitos, Calif., 1998, pp. 103-112.