SCOPUS 정보 검색 플랫폼

2004 Computing Frontiers Conference

Volumn , Issue , 2004, Pages 398-403

Platform-independent methodology for partial reconfiguration

(2) Koch, Dirk a Teich, Jürgen a

a UNIVERSITY OF ERLANGEN NUREMBERG (Germany)

Author keywords

Bitstream Extraction; Configuration Compression; Partial Reconfiguration

Indexed keywords

ALGORITHMS; BOOLEAN ALGEBRA; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA STRUCTURES; FIELD PROGRAMMABLE GATE ARRAYS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; STATIC RANDOM ACCESS STORAGE;

BITSTREAM EXTRACTIONS; CONFIGURATION COMPRESSIONS; PARTIAL RECONFIGURATIONS; PSEUDO-PARTIAL RECONFIGURATION (PPR);

COMPUTER SYSTEMS;

EID: 4143138809 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1145/977091.977148 Document Type: Conference Paper

Times cited : (14)

References (9)

1
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- Altrera Inc. webpage. www.altera.com.
- Altrera Inc. Webpage

2
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- Configuration compression for FPGA-based embedded systems
- A. Dandalis and V. K. Prasanna. Configuration compression for FPGA-based embedded systems. ACM/SIGDA Ninth International Symposium on FPGAs, pages 173-182, 2001.
- (2001) ACM/SIGDA Ninth International Symposium on FPGAs , pp. 173-182
- Dandalis, A.¹ Prasanna, V.K.²

3
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- Wrtenberger. Alternating run-length coding - A technique for improved test data compression
- October 10-11
- S. Hellebrand and A. Wrtenberger. Alternating run-length coding - a technique for improved test data compression. IEEE Workshop on Test Resource Partioning, October 10-11 2002.
- (2002) IEEE Workshop on Test Resource Partioning
- Hellebrand, S.¹ Wrtenberger, A.²

4
- 0036054393
- Dynamic hardware plugins in an fpga with partial run-time reconfiguration
- June 10-14
- E. L. Horta, J. W. Lockwood, D. E. Taylor, and D. Parlour. Dynamic hardware plugins in an fpga with partial run-time reconfiguration. 39th Design Automation Conference (DAC), New Orleans, LA, pages 262-171, June 10-14 2002.
- (2002) 39th Design Automation Conference (DAC), New Orleans, LA , pp. 262-1171
- Horta, E.L.¹ Lockwood, J.W.² Taylor, D.E.³ Parlour, D.⁴

5
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- Automated extraction of run-time parameterisable cores from programmable device configurations
- April
- P. James-Roxby and S. A. Guccione. Automated extraction of run-time parameterisable cores from programmable device configurations. IEEE Workshop on Field Programmable Custom Computing Machines, pages 153-161, April 2000.
- (2000) IEEE Workshop on Field Programmable Custom Computing Machines , pp. 153-161
- James-Roxby, P.¹ Guccione, S.A.²

6
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- Exploiting redundancy to speedup reconfiguration of an fpga
- September
- I. Kennedy. Exploiting redundancy to speedup reconfiguration of an fpga. 13th International Conference, FPL 2003, Lisbon, Portugal, pages 262-171, September 2003.
- (2003) 13th International Conference, FPL 2003, Lisbon, Portugal , pp. 262-1171
- Kennedy, I.¹

7
- 0032689815
- Don't care discovery for FPGA configuration compression
- Z. Li and S. Hauck. Don't Care Discovery for FPGA Configuration Compression. ACM/SIGDA International Symposium on FPGAs, pages 91-100, 1999.
- (1999) ACM/SIGDA International Symposium on FPGAs , pp. 91-100
- Li, Z.¹ Hauck, S.²

8
- 84963956653
- Configuration compression for virtex FPGAs
- Z. Li and S. Hauck. Configuration Compression for Virtex FPGAs. IEEE Symposium on Field-Programmable Custom Computing Machines, 2001.
- (2001) IEEE Symposium on Field-Programmable Custom Computing Machines
- Li, Z.¹ Hauck, S.²

9
- 4143071590
- JBits 2.0.1 documentation
- Xilinx Inc. JBits-Java Based APIs. JBits 2.0.1 documentation, 1999.
- (1999) JBits-java Based APIs

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