Repeater and interconnect strategies for high-performance physical designs

Proceedings - 11th Brazilian Symposium on Integrated Circuit Design, SBCCI 1998

Volumn 1998-September, Issue , 1998, Pages 226-231

  Muddu, S ^a   Sarto, E ^a   Hofmann, M ^a   Bashteen, A ^a  

^a HEWLETT PACKARD ENTERPRISE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE; TELECOMMUNICATION REPEATERS; TUNING;

INTERCONNECT DELAY; INTERCONNECT PERFORMANCE; LINEAR FUNCTIONS; MANUFACTURABILITY; OPTIMUM TECHNIQUE; REPEATER INSERTION; SIGNAL PERFORMANCE; TOTAL PATH LENGTH;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 40949140396     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.1998.715447     Document Type: Conference Paper

References (14)

1. Semiconductor Industry Association, National Technology Roadmap for Semiconductors, 1994.
2. Personal communication, SIA NTRS 1997 Revision, Design and Test TechnologyWorking Group (chairs: R. Howard, P. Verhofstadt), 1997.
3. C. J. Alpert and A. Devgan,"Wire Segmenting for Improved Buffer Insertion", Proc. Design Automation Conf., June 1997.
4. A. Deutsch, G. V. Kopcsay, C. W. Surovic, B. J. Rubin, L. M. Terman, R. P. Dunne and T. Gallo, "Modeling and Characterization of Long Onchip Interconnections for High-Performance Microprocessors", final report, ARPA HSCD Contract C-556003, September 1995. Also appeared in IBM Journal of Research and Development 39(5), Sept. 1995, pp. 547-567.
5. P. D. Fisher, "Clock Cycle Estimations for Future MicroprocessorGenerations", manuscript (to be published), July 1997.
6. L. Gwennap, "IC Makers Confront RC Limitations", Microdesign Resources MicroprocessorReport, August 4, 1997, pp. 14-18.
7. D. P. LaPotin, U. Ghoshal, E. Chiprout and S. R. Nassif, "PhysicalDesign Challenges for Performance", International Symposium on Physical Design, April 1997, pp. 225-226.
8. J. Meindl, "GigaScale Integration: 'Is the Sky the Limit'?", keynote presentation slides, Hot Chips IX, Stanford, CA, August 25-26, 1997.
9. L. Scheffer, "A Roadmap of CAD Tool Changes for Sub-micron Interconnect Problems", International Symposiumon PhysicalDesign,April 1997, pp. 104-109.
10. R. F. Sechler, "Interconnect design with VLSI CMOS", IBM Journal of Research and Development, Jan.-March 1995, pp. 23-31.
11. J. Cong, L. He, A. B. Kahng,D. Noice,N. Shirali and S. H.-C. Yen, "Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology", Proc. Design Automation Conference, June 1997.
12. L. Gwennap, "ICVendors Prepare for 0.25-MicronLeap", Microprocessor Report, September 16, 1996, pp. 11-15.
13. A. B. Kahng and S. Muddu, "Efficient gate Delay Modeling for Large Interconnect Loads", Proc. IEEE Multi-Chip Module Conf., Feb. 1996.
14. S.-Y. Oh, K.-J. Chang, N. Chang and K. Lee, "Interconnectmodeling and design in high-speed VLSI/ULSI systems", Proc. International Conference on Computer Design: VLSI in Computers and Processors, October 1992, pp. 184-189.