A 0.8-mW 55-GHz dual-injection-locked CMOS frequency divider

IEEE Transactions on Microwave Theory and Techniques

Volumn 56, Issue 3, 2008, Pages 620-625

  Luo, Tang Nian ^a,b   Chen, Yi Jan Emery ^a,b  

^a IEEE

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

CMOS; Frequency divider; Injection locked; Locking range; Millimeter wave

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; MILLIMETER WAVE DEVICES; NATURAL FREQUENCIES; RESONATORS; VARACTORS;

FREQUENCY DIVIDERS; INJECTION LOCKED; LOCKING RANGE;

FREQUENCY DIVIDING CIRCUITS;

EID: 40549123408     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2008.916868     Document Type: Article

References (24)

1. J. M. C. Wong, V. S. L. Cheung, and H. C. Luong, "A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-μm CMOS process," IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1643-1648, Oct. 2003.
2. A. Rylyakov and T. Zwick, "96-GHz static frequency divider in SiGe bipolar technology," IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1712-1715, Oct. 2004.
3. K. Washio, R. Hayami, E. Ohue, K. Oda, M. Tanabe, H. Shimamoto, and M. Kondo, "67-GHz static frequency divider using 0.2-μm self-aligned SiGe HBTs," IEEE Trans. Microw. Theory Tech., vol. 49, no. 1, pp. 3-8, Jan. 2001.
4. M. Mokhtari, C. Fields, R. D. Rajavel, M. Sokolich, J. F. Jensen, and W. E. Stanchina, " 100 + GHz static divide-by-2 circuit in InP-DHBT technology," IEEE J. Solid-State Circuits, vol. 38, no. 9, pp. 1540-1544, Sep. 2003.
5. P. Heydari and R. Mohanavelu, "A 40-GHz flip-flop-based frequency divider," IEEE Trans. Cirvuits Syst. II, Analog Digit. Signal Process., vol. 53, no. 12, pp. 1358-1362, Dec. 2006.
6. Y. Yamauchi, O. Nakajima, K. Nagata, and M. Hirayama, "A 15-GHz monolithic two-modulus prescaler," IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1632-1636, Nov. 2001.
7. U. Singh and M. M. Green, "High-Frequency CML clock dividers in 0.13-μm. CMOS operating up to 38 GHz," IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1658-1661, Aug. 2005.
8. K. Yamamoto and M. Fujishima, "A 44-μW 4.3-GHz injection-locked frequency divider with 2.3-GHz locking range," IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 671-677, Mar. 2005.
9. W.-Z. Chen and C. Liang, "18 GHz and 7 GHz superharmonic injection-locked dividers in 25 μm CMOS technology," in Proc. 28th Eur. Solid-State Circuits Conf., Sep. 2002, pp. 89-92.
10. M. Kurisu, G. Uemura, M. Ohuchi, C. Ogawa, H. Takemura, T. Morikawa, and T. Tashiro, "A Si bipolar 28-GHz dynamic frequency divider," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1799-1804, Dec. 1992.
11. J. Jeong and Y. Kwon, "V-band high-order harmonic injection-locked frequency-divider MMICs with wide bandwidth and low-power dissipation," IEEE Trans. Microw. Theory Tech., vol. 53, no. 6, pp. 1891-1898, Jun. 2005.
12. K. Kanazawa, M. Hagio, M. Kazumura, and G. Kano, "A 15 GHz single-stage GaAs dual-gate FET monolithic analog frequency divider with reduced input threshold power," IEEE Trans. Microw. Theory Tech., vol. 36, no. 12, pp. 1908-1912, Dec. 1988.
13. R. H. Derksen and H.-M. Rein, "7.3-GHz dynamic frequency dividers monolithically integrated in a standard bipolar technology," IEEE Trans. Microw. Theory Tech., vol. 36, no. 3, pp. 537-541, Mar. 1988.
14. S. Kudszus, W. H. Haydl, M. Neumann, and M. Schlechtweg, "94/47-GHz regenerative frequency divider MMIC with low conversion loss," IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1312-1317, Sep. 2000.
15. J.-C. Sarkissian, M. Camiade, P. Savary, A. Suarez, R. Quere, and J. Obregon, "A 60-GHz HEMT-MMIC analog frequency divider by two," IEEE J. Solid-State Circuits, vol. 30, no. 10, pp. 1062-1067, Oct. 1995.
16. J. Lee and B. Razavi, "A 40-GHz frequency divider in 0.18-μm CMOS technology," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 594-601, Apr. 2004.
17. Y.-J. E. Chen, S.-Y. Bai, T.-N. Luo, Y.-H. Yu, and D. Heo, "A wide operation range CMOS frequency divider for 60 GHz dual-conversion receiver," in IEEE RFIC Tech. Symp. Dig., Jun. 2006, 4 pp.
18. H. R. Rategh and T. H. Lee, "Superharmonic injection-locked frequency dividers," IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813-821, Jun. 1999.
19. H. Wu and A. Hajimiri, "A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement," in IEEE Int. Solid-State Circuits Conf., Feb. 2001, pp. 412-413, 417.
20. K. Yamamoto and M. Fujishima, "55 GHz CMOS frequency divider with 3.2 GHz locking range," in Proc. 30th Eur. Solid-State Circuits Conf., Sep. 2004, pp. 135-138.
21. B. Razavi, "A study of injection locking and pulling in oscillator," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, Sep. 2004.
22. M. Tiebout, "A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider," IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 1170-1174, Mar. 2005.
23. K. Yamamoto and M. Fujishima, "70 GHz CMOS harmonic injection locked divider," in IEEE Int. Solid-State Circuits Conf., Feb. 2006, pp. 2472-2481.
24. S.-Y. Bai, "Design of CMOS frequency dividers for 60 GHz applications," M.S., Graduate Inst. Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 2007.