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Volumn 3569, Issue , 2005, Pages 444-450

FPGA logic synthesis using quantified boolean satisfiability

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; FIELD PROGRAMMABLE GATE ARRAYS;

EID: 26444482893     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11499107_37     Document Type: Conference Paper
Times cited : (23)

References (11)
  • 3
    • 26444585035 scopus 로고    scopus 로고
    • MVSIS 2.0 programmer's manual
    • Electrical Engineering and Computer Sciences, University of California, Berkeley
    • D. Chai, J. Jiang, Y. Jiang, Y. Li, A. Mishchenko, and R. Brayton. MVSIS 2.0 Programmer's Manual, UC Berkeley. Technical report, Electrical Engineering and Computer Sciences, University of California, Berkeley, 2003.
    • (2003) UC Berkeley. Technical Report
    • Chai, D.1    Jiang, J.2    Jiang, Y.3    Li, Y.4    Mishchenko, A.5    Brayton, R.6
  • 4
    • 0029712690 scopus 로고    scopus 로고
    • RASP: A general logic synthesis system for SRAM-based FPGAs
    • J. Cong, J. Peck, and Y. Ding. RASP: A general logic synthesis system for SRAM-based FPGAs. In FPGA, pages 137-143, 1996.
    • (1996) FPGA , pp. 137-143
    • Cong, J.1    Peck, J.2    Ding, Y.3
  • 6
    • 0026623575 scopus 로고
    • Test pattern generation using boolean satisfiablity
    • T. Larrabee. Test Pattern Generation Using Boolean Satisfiablity. IEEE Transactions on Computer-Aided Design, 11(1):6-22, 1992.
    • (1992) IEEE Transactions on Computer-aided Design , vol.11 , Issue.1 , pp. 6-22
    • Larrabee, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.