A 1.5V, 1.6Gb/s/pin, 1Gb DDR3 SDRAM with an address queuing scheme and bang-bang jitter reduced DLL scheme

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 182-183

  Kim, Yang Ki ^a   Jeon, Young Jin ^a   Jeong, Byung Hoon ^a   Heo, Nak Won ^a   Chang, Soo Bong ^a   Jung, Han Gyun ^a   Kim, Doo Young ^a   Chung, Hoe Ju ^a   Kim, Chul Soo ^a   Ko, Seung Bum ^a   Kyung, Kye Hyun ^a   Yoo, Jei Hwan ^a   Cho, Soo In ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; JITTER; QUEUEING NETWORKS;

BANG-BANG JITTER; PHASE INTERPOLATORS; QUEUING SCHEME;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 39749145232     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342706     Document Type: Conference Paper

References (4)

1. C. Park, et al., "A 512-Mb DDR3 SDRAM. Prototype with CIO Minimization and Self-Calibration Techniques," IEEE J. of Solid-State Circuits, pp. 831-841, April, 2006.
2. B. Nikolic, et al., "Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements," IEEF, J. of Solid-State Circuits, pp. 876-884, June, 2000.
3. G. A. Allen, "Self-Timed Device and Method," US Patent 5,729,160, Mar. 17, 1988.
4. K. Kim, et al., "A 1.4Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2004, pp 212-223