A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2007, Pages 397-400

  Lin, Yu Shiang ^a   Sylvester, Dennis ^a   Blaauw, David ^a  

^a Department of Ecology and Evolutionary Biology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ENERGY DISSIPATION; LEAKAGE CURRENTS;

GATE LEAKAGE; SUBTHRESHOLD SYSTEMS;

GATE DIELECTRICS;

EID: 39549097181     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405761     Document Type: Conference Paper

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