A low-power integrated bioamplifier with active low-frequency suppression

IEEE Transactions on Biomedical Circuits and Systems

Volumn 1, Issue 3, 2007, Pages 184-192

  Gosselin, Benoit ^a   Sawan, Mohamad ^a   Chapman, C Andrew ^b  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

^b and Applied Physiology   (Canada)

Author keywords

Active low frequency suppression; Biopotential recording; Dense integrated neural interfaces; Integrated bioamplifier; Micropower analog circuit design

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; CUTOFF FREQUENCY; ELECTRIC IMPEDANCE; RESISTORS; TRANSCONDUCTANCE; TRANSFER FUNCTIONS;

ACTIVE LOW-FREQUENCY SUPPRESSION; BIOPOTENTIAL RECORDING; DENSE INTEGRATED NEURAL INTERFACES; INTEGRATED BIOAMPLIFIER;

BIOMEDICAL EQUIPMENT;

EID: 39549086320     PISSN: 19324545     EISSN: None     Source Type: Journal    
DOI: 10.1109/TBCAS.2007.914490     Document Type: Article

References (29)

1. Q. Bai and K. D. Wise, "Single-unit neural recording with active microelectrode arrays," IEEE Trans. Biomed. Eng., vol. 48, no. 8, pp. 911-920, Aug. 2001.
2. R. H. Olsson, III and K. D. Wise, "A three-dimensional neural recording microsystem with implantable data compression circuitry," IEEE J. Solid-State Circuits, vol. 40, pp. 2796-2804, Dec. 2005.
3. S. Yoon-Kyu et al., "Development of a chipscale integrated microelectrode/microelectronic device for brain implantable neuroengineering applications," IEEE Trans. Neural Syst. Rehab. Eng. vol. 13, no. 2, pp. 220-6, Jun. 2005.
4. R. R. Harrison et al., "A low-power integrated circuit for a wireless 100-Electrode neural recording system," IEEE J. Solid-State Circuits, vol. 42, pp. 123-133, 2007.
5. Y. Perelman and R. Ginosar, "An integrated system for multichannel neuronal recording with spike/LFP separation, integrated A/D conversion and threshold detection," IEEE Trans. Biomed. Eng., vol. 54, pp. 130-137, 2007.
6. G. Buzsaki, "Large-scale recording of neuronal ensembles," Nat. Neurosci., vol. 7, pp. 446-51, 2004.
7. J. K. Chapin, "Using multineuron population recordings for neural prosthetics," Nat. Neurosci., vol. 7, pp. 452-5, 2004.
8. L. R. Hochberg et al., "Neuronal ensemble control of prosthetic devices by a human with tetraplegia," Nature, vol. 442, pp. 164-71, 2006.
9. M. A. Lebedev and M. A. Nicolelis, "Brain-machine interfaces: Past, present and future," Trends Neurosci., vol. 29, pp. 536-46, 2006.
10. E. H. Liu, G. M. Saidel, and H. Harasaki, "Model analysis of tissue responses to transient and chronic heating," Ann. Biomed. Eng., vol. 31, pp. 1007-14, 2003.
11. A. P. Chandran, K. Najafi, and K. D. Wise, "A new dc baseline stabilization scheme for neural recording microprobes," in Proc. 1st Joint BMES/EMBS Conf., 1999, pp. 386-386.
12. R. R. Harrison and C. Charles, "A low-power low-noise CMOS amplifier for neural recording applications," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 958-65, Jun. 2003.
13. M. Mojarradi et al., "A miniaturized neuroprosthesis suitable for implantation into the brain," IEEE Trans. Neural Syst. Rehab. Eng. vol. 11, pp. 38-42, 2003.
14. C. Du, J. G. Harris, and J. C. Principe, "A bio-amplifier with pulse output," in Proc. 26th Ann. Int. Conf. Eng. Med. Biol. Soc., 2004, pp. 4071-4074.
15. P. Mohseni and K. Najafi, "A fully integrated neural recording amplifier with DC input stabilization," IEEE Trans. Biomed. Eng., vol. 51, no. 5, pp. 832-837, May 2004.
16. E. M. Spinelli, N. Martinez, M. A. Mayosky, and R. Pallas-Areny, "A novel fully differential biopotential amplifier with DC suppression," IEEE Trans. Biomed. Eng., vol. 51, no. 8, pp. 1444-1448, Aug. 2004.
17. T. Degen and H. Jackel, "A pseudodifferential amplifier for bioelectric events with DC-offset compensation using two-wired amplifying electrodes," IEEE Trans. Biomed. Eng., vol. 53, no. 2, pp. 300-310, Feb. 2006.
18. B. Gosselin, A. E. Ayoub, and M. Sawan, "A low-power bioamplifier with a new active DC rejection scheme," in Proc. 2006 IEEE Int. Symp. Circuits Syst., 2006, pp. 2185-2188.
19. T. Delbruck and C. A. Mead, "Adaptive photoreceptor with wide dynamic range," in Proc. 1994 IEEE Int. Symp. Circuits Syst., 1994, pp. 339-342.
20. R. J. Baker, CMOS: Circuit Design, Layout, and Simulation, 2nd ed. New York: Wiley-IEEE, 2005.
21. E. A. Vittoz, "Micropower techniques," in Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, J. E. Franca and Y. Tsividis, Eds. Upper Saddle River, NJ: Prentice-Hall, 1994, pp. 53-96.
22. C. Enz, F. Krummenacher, and E. A. Vittoz, "An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications," Analog Integr. Circuits Signal Process., vol. 8, pp. 83-114, 1995.
23. D. M. Binkley, B. J. Blalock, and J. M. Rochelle, "Optimizing drain current, inversion level, and channel length in analog CMOS design," Analog Integr. Circuits Signal Proc.ess, vol. 47, pp. 137-163, 2006.
24. A. J. Scholten et al., "Noise modeling for RF CMOS circuit simulation," IEEE Tran. Electron Devices, vol. 50, no. 3, pp. 618-632, Mar. 2003.
25. A. Arnaud and C. Galup-Montoro, "Consistent noise models for analysis and design of CMOS circuits," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 10, pp. 1909-1915, Oct. 2004.
26. A. S. Roy and C. Enz, "Compact modeling of thermal noise in the MOS transistor," IEEE Trans. Electron Devices, vol. 52, no. 4, pp. 611-614, Apr. 2005.
27. D. J. Frank et al., "Device scaling limits of SI MOSFETs and their application dependencies," Proc. IEEE, vol. 89, no. 3, pp. 259-288, Mar. 2001.
28. T. M. Hollis, D. J. Comer, and D. T. Comer, "Optimization of MOS amplifier performance through channel length and inversion level selection," IEEE Trans. Circuits Systems. II, Exp. Briefs, vol. 52, no. 9, pp. 545-549, Sep. 2005.
29. M. C. Schneider, C. Galup-Montero, O. C. G. Filho, and A. I. A. Cunha, "A single-piece charge-based model for the output conductance of MOS transistors," in Proc. IEEE Int. Conf. Electron., Circuits Syst., 1998, pp. 545-548.