Integration of CVD silicon nanocrystals in a 32Mb NOR flash memory

ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference

Volumn 2007, Issue , 2007, Pages 410-413

  Jacob, S ^a,b   Festes, G ^a   Bodnar, S ^a   Coppard, R ^a   Thiery, J F ^a   Pate Cazal, T ^a   Pedron, T ^a   De Salvo, B ^b   Perniola, L ^b   Jalaguier, E ^b   Boulanger, F ^b   Deleonibus, S ^b  

^a ATMEL Rousset   (France)

^b CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL VAPOR DEPOSITION; FLASH MEMORY; ROBUSTNESS (CONTROL SYSTEMS); SILICON;

ARRAY VOLTAGE DISTRIBUTION WIDTHS; DATA RETENTION; NOR FLASH MEMORY;

NANOCRYSTALS;

EID: 39549085553     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2007.4430965     Document Type: Conference Paper

References (6)

1. B. De Salvo et al., " How far will Silicon nanocrystals push the scaling limits of NVMs technologies?", Techn. Dig. of IEDM, p. 597, 2003.
2. R. Muralidhar et al., "A 6V Embedded 90nm Silicon Nanocrystal Nonvolatile Memory", Techn. Dig. of IEDM, p. 601, 2003.
3. G. Ammendola et al., "Nanocrystal memories for FLASH device applications", Solid-State Electronics, vol. 48, p. 1483, 2004.
4. B. De Salvo et al., "Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS)", IEEE Trans. Device Mater. Rel., vol; 4, p. 377, 2004.
5. S. Lombardo et al., "Distribution of the Threshold Voltage Window in Nanocrystal Memories with Si Dots Formed by Chemical Vapor Deposition: Effect of Partial Self-Ordering", IEEE Non Volatile Semiconductor Memory Workshop, p. 69, 2004.
6. B. De Salvo et al., "Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices", IEEE Trans. on Electa. Dev, vol. 48, p. 1789, 2001.