A digital PLL with 5-phase digital PFD for low long-term jitter clock recovery

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2006, Pages 745-748

  Oh, Tae Young ^a   Yi, Seung Hyun ^a   Yang, Sung Hyun ^a   Lim, Byong Chan ^a   Hong, Kuk Tae ^a  

^a LG Electronics Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; NATURAL FREQUENCIES; OSCILLATORS (ELECTRONIC);

DIGITAL PHASE FREQUENCY; DIGITAL PLL; JITTER CLOCK RECOVERY;

JITTER;

EID: 39049086225     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320966     Document Type: Conference Paper

References (4)

1. L. Xiu, W. Li and J. Meiners, "A Novel All-Digital PLL With Software Adaptive Filter," IEEE JSSC, VOL. 39, No. 3, pp. 476483, Mar. 2004.
2. A.M. Fahim, "A compact, low-power low-jitter digital PLL," ESSCIRC, pp. 101-104, Sep. 2003.
3. T. Olosson and P. Nilsson "A Digitally Controlled PLL for SOC Applications," IEEE JSSC, VOL. 39, No. 5, pp. 751-760, May 2004.
4. T. Watanabe and S. Yamauchi "An All-Digital PLL for Frequency Multiplication by 4 to 1022 With Seven-Cycle Lock Time", IEEE JSSC, VOL. 38, No. 2, pp. 198-204, Feb 200