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Volumn 37, Issue 11, 2002, Pages 1502-1509

High-performance 1-Gb NAND flash memory with 0.12-μm technology

Author keywords

32 cell NAND structure; Cache program; CMOS memory integrated circuits; EEPROM; Flash memory; NAND flash memory; Page copy back; Pseudo 4 phase charge pump

Indexed keywords

CACHE MEMORY; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT MANUFACTURE; POWER SUPPLY CIRCUITS;

EID: 0036858571     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.802352     Document Type: Article
Times cited : (15)

References (9)
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  • 2
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    • Feb
    • J. Lee, et al., "A 1.8V 1-Gb NAND flash memory with 0.12-μm STI process technology," in ISSCC Dig. Tech. Papers, Feb. 2002, pp. 104-105.
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    • Lee, J.1
  • 4
    • 0031340143 scopus 로고    scopus 로고
    • Floating-well charge pump circuits for sub-2.0V single power supply flash memories
    • K.-H. Choi et al., "Floating-well charge pump circuits for sub-2.0V single power supply flash memories," in Symp. VLSI Circuits Dig. Tech. Papers, June 1997, pp. 61-62.
    • Symp. VLSI Circuits Dig. Tech. Papers, June 1997 , pp. 61-62
    • Choi, K.-H.1
  • 5
    • 0029251968 scopus 로고
    • A 3.3V 32Mb NAND flash memory with incremental step pulse programming scheme
    • Nov
    • K. D. Suh et al., "A 3.3V 32Mb NAND flash memory with incremental step pulse programming scheme," IEEE J. Solid-State Circuits, vol. 30, pp. 1149-1156, Nov. 1995.
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  • 6
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    • Feb
    • 2 1Gb NAND flash memory with 10MB/s program throughput," in ISSCC Dig. Tech. Papers, Feb. 2002, pp. 106-107.
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  • 7
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    • 2, 256Mb NAND flash with shallow trench isolation technology
    • Feb
    • 2, 256Mb NAND flash with shallow trench isolation technology," in ISSCC Dig. Tech. Papers, Feb. 1999, pp. 112-113.
    • (1999) ISSCC Dig. Tech. Papers , pp. 112-113
    • Imamiya, K.1
  • 8
    • 0028538112 scopus 로고
    • A quick intelligent page-programming architecture and a shielded bitline sensing method for 3V-only NAND flash memory
    • Nov
    • T. Tanaka et al., "A quick intelligent page-programming architecture and a shielded bitline sensing method for 3V-only NAND flash memory," IEEE J. Solid-State Circuits, vol. 29, pp. 1149-1156, Nov. 1994.
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  • 9
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    • A source-line programming scheme for low-voltage operation NAND flash memories
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    • K. Takeuchi et al., "A source-line programming scheme for low-voltage operation NAND flash memories," IEEE J. Solid-State Circuits, vol. 35, pp. 672-681, May 2000.
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    • Takeuchi, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.