-
1
-
-
38649086028
-
-
DDJ Microprocessor Center, Online, Available
-
DDJ Microprocessor Center. [Online]. Available: http://www.x86.org/
-
-
-
-
2
-
-
38649091751
-
-
Online, Available
-
QIfdiv (Enable Pentium FDIV Fix). [Online]. Available: http://msdn2.microsoft.com/en_us/library/ms856573.aspx
-
QIfdiv (Enable Pentium FDIV Fix)
-
-
-
5
-
-
38649141907
-
-
Intel(R) Pentium(R) II Processor Invalid Instruction Erratum Overview, Jul. 2002.
-
Intel(R) Pentium(R) II Processor Invalid Instruction Erratum Overview, Jul. 2002.
-
-
-
-
7
-
-
38649117989
-
-
Intel(R) Pentium(R) Processor Invalid Instruction Erratum Overview, Jul. 2004.
-
Intel(R) Pentium(R) Processor Invalid Instruction Erratum Overview, Jul. 2004.
-
-
-
-
8
-
-
38649133405
-
-
IBM PowerPC 750GX and 750GL RISC Microprocessor Errata Notice, Jul
-
IBM PowerPC 750GX and 750GL RISC Microprocessor Errata Notice, Jul. 2005.
-
(2005)
-
-
-
9
-
-
38649084155
-
-
Intel(R) Pentium(R) III Processor Specification Update, May
-
Intel(R) Pentium(R) III Processor Specification Update, May 2005.
-
(2005)
-
-
-
11
-
-
0036149148
-
Technology roadmap for semiconductors
-
Jan
-
A. Allan, D. Edenfeld, J. William, H. Joyner, A. B. Kahng, M. Rodgers, and Y. Zorian, "2001 Technology roadmap for semiconductors," Computer, vol. 35, no. 1, pp. 42-53, Jan. 2002.
-
(2001)
Computer
, vol.35
, Issue.1
, pp. 42-53
-
-
Allan, A.1
Edenfeld, D.2
William, J.3
Joyner, H.4
Kahng, A.B.5
Rodgers, M.6
Zorian, Y.7
-
12
-
-
26444578155
-
Validating a modern microprocessor
-
Jul
-
B. Bentley, "Validating a modern microprocessor," in Proc. Int. Conf. CAV, Jul. 2005, pp. 2-4.
-
(2005)
Proc. Int. Conf. CAV
, pp. 2-4
-
-
Bentley, B.1
-
13
-
-
0142206120
-
Validating the Intel Pentium 4 microprocessor
-
Feb
-
B. Bentley and R. Gray, "Validating the Intel Pentium 4 microprocessor," Intel Technol. J., vol. 5, no. 1, pp. 1-8, Feb. 2001.
-
(2001)
Intel Technol. J
, vol.5
, Issue.1
, pp. 1-8
-
-
Bentley, B.1
Gray, R.2
-
14
-
-
38649117340
-
Moving atom to Windows NT for alpha
-
Jan
-
E. B. Brett, D. P. Hunter, and S. L. Smith, "Moving atom to Windows NT for alpha," Compaq DIGITAL Tech. J., vol. 10, no. 2, Jan. 1999.
-
(1999)
Compaq DIGITAL Tech. J
, vol.10
, Issue.2
-
-
Brett, E.B.1
Hunter, D.P.2
Smith, S.L.3
-
15
-
-
0343371798
-
Collection and analysis of microprocessor design errors
-
Oct.-Dec
-
D. Van Campenhout, T. Mudge, and J. P. Hayes, "Collection and analysis of microprocessor design errors," IEEE Des. Test Comput., vol. 17, no. 4, pp. 51-60, Oct.-Dec. 2000.
-
(2000)
IEEE Des. Test Comput
, vol.17
, Issue.4
, pp. 51-60
-
-
Van Campenhout, D.1
Mudge, T.2
Hayes, J.P.3
-
16
-
-
0004301377
-
Scan mechanism for monitoring the state of internal signals of a VLSI microprocessor chip,
-
U.S. Patent 5 253 255, Nov
-
A. Carbine, "Scan mechanism for monitoring the state of internal signals of a VLSI microprocessor chip," U.S. Patent 5 253 255, Nov. 1990.
-
(1990)
-
-
Carbine, A.1
-
17
-
-
33845331515
-
Minimization of Boolean functions
-
Nov
-
E. J. McCluskey, "Minimization of Boolean functions," Bell Syst Tech. J., vol. 6, no. 35, pp. 1417-1444, Nov. 1956.
-
(1956)
Bell Syst Tech. J
, vol.6
, Issue.35
, pp. 1417-1444
-
-
McCluskey, E.J.1
-
18
-
-
0019339514
-
High level language programs run ten times faster in microstore
-
J. Henry, G. Baker, and C. Parker, "High level language programs run ten times faster in microstore," in Proc. 13th Annu. Workshop Microprogramming, 1980, pp. 171-177.
-
(1980)
Proc. 13th Annu. Workshop Microprogramming
, pp. 171-177
-
-
Henry, J.1
Baker, G.2
Parker, C.3
-
19
-
-
0034480956
-
Smart simulation using collaborative formal and simulation engines
-
P. H. Ho, T. Shiple, K. Harer, J. Kukula, R. Damiano, V. Bertacco, J. Taylor, and J. Long, "Smart simulation using collaborative formal and simulation engines," in Proc. ICCAD, 2000, pp. 120-126.
-
(2000)
Proc. ICCAD
, pp. 120-126
-
-
Ho, P.H.1
Shiple, T.2
Harer, K.3
Kukula, J.4
Damiano, R.5
Bertacco, V.6
Taylor, J.7
Long, J.8
-
20
-
-
33751405916
-
Simulation-based bug trace minimization with BMC-based refinement
-
Nov
-
K. H. Chang, V. Bertacco, and I. Markov, "Simulation-based bug trace minimization with BMC-based refinement," in Proc. ICCAD, Nov. 2005, pp. 1045-1051.
-
(2005)
Proc. ICCAD
, pp. 1045-1051
-
-
Chang, K.H.1
Bertacco, V.2
Markov, I.3
-
21
-
-
38649090438
-
Microcode patch device and method for patching microcode using match registers and patch routines,
-
U.S. Patent 6 438 664, Oct
-
J. K. P. Kevin and J. McGrath, "Microcode patch device and method for patching microcode using match registers and patch routines," U.S. Patent 6 438 664, Oct. 1999.
-
(1999)
-
-
Kevin, J.K.P.1
McGrath, J.2
-
23
-
-
38649134855
-
Microcode patching apparatus and method,
-
U.S. Patent 5 796 974, Nov
-
M. D. Goddard and D. S. Christie, "Microcode patching apparatus and method," U.S. Patent 5 796 974, Nov. 1995.
-
(1995)
-
-
Goddard, M.D.1
Christie, D.S.2
-
24
-
-
34249788697
-
-
S. Sarangi, S. Narayanasamy, B. Carneal, A. Tiwari, B. Calder, and J. Torrellas, Patching processor design errors with programmable hardware, IEEE Micro - Special. Issue: Micro's Top Picks from Computer Architecture Conferences, 27, no. 1, pp. 12-25, Jan./Feb. 2007.
-
S. Sarangi, S. Narayanasamy, B. Carneal, A. Tiwari, B. Calder, and J. Torrellas, "Patching processor design errors with programmable hardware," IEEE Micro - Special. Issue: Micro's Top Picks from Computer Architecture Conferences, vol. 27, no. 1, pp. 12-25, Jan./Feb. 2007.
-
-
-
-
25
-
-
3142766211
-
ATOM: A system for building customized program analysis tools
-
Apr
-
A. Srivastava and A. Eustace, "ATOM: A system for building customized program analysis tools," ACM SIGPLAN Not., vol. 39, no. 4, pp. 528-539, Apr. 2004.
-
(2004)
ACM SIGPLAN Not
, vol.39
, Issue.4
, pp. 528-539
-
-
Srivastava, A.1
Eustace, A.2
-
26
-
-
27944434994
-
StressTest: An automatic approach to test generation via activity monitors
-
I. Wagner, V. Bertacco, and T. Austin, "StressTest: An automatic approach to test generation via activity monitors," in Proc. DAC, 2005, pp. 783-788.
-
(2005)
Proc. DAC
, pp. 783-788
-
-
Wagner, I.1
Bertacco, V.2
Austin, T.3
-
27
-
-
34547226732
-
Shielding against design flaws with field repairable control logic
-
I. Wagner, V. Bertacco, and T. Austin, "Shielding against design flaws with field repairable control logic," in Proc. DAC, 2006, pp. 344-347.
-
(2006)
Proc. DAC
, pp. 344-347
-
-
Wagner, I.1
Bertacco, V.2
Austin, T.3
|