Word-level predicate-abstraction and refinement techniques for verifying RTL verilog

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 2, 2008, Pages 366-379

  Jain, Himanshu ^b   Kroening, Daniel ^c   Sharygina, Natasha ^d   Clarke, Edmund M ^a,b  

^a IEEE

^b Carnegie Mellon University ^*  (United States)

^c UNIVERSITY OF OXFORD   (United Kingdom)

^d UNIVERSITY OF LUGANO   (Switzerland)

Author keywords

Model checking (MC); Predicate abstraction; Refinement; Register transfer level (RTL); Satisfiability (SAT); Verification

Indexed keywords

CLUSTERING ALGORITHMS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SOFTWARE; DIGITAL ARITHMETIC; MODEL CHECKING;

PREDICATE ABSTRACTION; REGISTER TRANSFER LEVEL (RTL); SATISFIABILITY (SAT);

ABSTRACTING;

EID: 38649118182     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.907270     Document Type: Article

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