Automatic abstraction and verification of verilog models

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 218-223

  Andraus, Zaher S ^a   Sakallah, Karem A ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Abstraction; Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions (CLU); Register Transfer Level (RTL); UCLID; Verilog

Indexed keywords

ABSTRACTING; BINARY CODES; COMPUTER HARDWARE; ENCODING (SYMBOLS); SEMANTICS; VECTORS;

ABSTRACTION; REGISTER TRANSFER LEVEL (RTL); UCLID; VERILOG;

LOGIC CIRCUITS;

EID: 4444280802     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996629     Document Type: Conference Paper

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