Word level predicate abstraction and refinement for verifying RTL Verilog

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 445-450

  Jain, Himanshu ^a   Sharygina, Natasha ^a   Kroening, Daniel ^b   Clarke, Edmund ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b ETH ZURICH   (Switzerland)

Author keywords

Predicate Abstraction; SAT; Verilog

Indexed keywords

COMPUTER SOFTWARE; HARDWARE; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); PROBLEM SOLVING; STATE SPACE METHODS; WORD PROCESSING;

PREDICATE ABSTRACTION; SAT; VERILOG;

ABSTRACTING;

EID: 27944469105     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1065579.1065697     Document Type: Conference Paper

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