Architectural exploration of heterogeneous multiprocessor systems for JPEG

International Journal of Parallel Programming

Volumn 36, Issue 1, 2008, Pages 140-162

  Shee, Seng Lin ^a,b   Erdos, Andrea ^a   Parameswaran, Sri ^a,b  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

^b CSIRO   (Australia)

Author keywords

Architecture; ASIPs; Design; Heterogeneous system; Multiprocessor; Pipelines; SoC

Indexed keywords

HETEROGENEOUS SYSTEM; IMAGE ENCODING; MULTIPROCESSORS; SINGLE MULTITASKING CORE;

IMAGE PROCESSING; MULTIPROCESSING SYSTEMS; MULTITASKING; PIPELINES;

COMPUTER ARCHITECTURE;

EID: 38349175054     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10766-007-0040-7     Document Type: Article

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