A tool for partitioning and pipelined scheduling of hardware-software systems

Proceedings of the International Symposium on System Synthesis

Volumn Part F129250, Issue , 1998, Pages 145-151

  Chatha, Karam S ^a   Vemuri, Ranga ^a  

^a University of Cincinnati   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BRANCH AND BOUND METHOD; COMPUTER SOFTWARE; ITERATIVE METHODS; SCHEDULING;

BRANCH-AND-BOUND APPROACHES; HARDWARE SOFTWARE PARTITIONING; HARDWARE-SOFTWARE SYSTEMS; MEMORY REQUIREMENTS; OBJECTIVE FUNCTIONS; PARTITIONING ALGORITHMS; PIPELINED IMPLEMENTATION; PIPELINED SCHEDULING;

PIPELINES;

EID: 84956858975     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isss.1998.730616     Document Type: Conference Paper

References (15)

1. S. Bakshi and D.D. Gajski, "Hardware/SoftwarePartitioning and Pipelining, " Proceeding of 34th Design Automation Conference, Anaheim, CA, June 1997.
2. S. Bakshi and D.D. Gajski, "A Scheduling and Pipelining Algorithm for Hardware/Software Systems, " Proceedings of 10th International Symposium on System Synthesis, Antwerp, Belgium, September 1997.
3. P. Bjorn-Jorgensen and J. Madsen, "Critical Path Driven Cosynthesis for Heterogeneous Target Architectures, ", Proceedings of Fifth International Workshop on Hardware/Software Codesign, Braunschweig, Germany, March 1997.
4. L-Fang Chao, A. S. LaPaugh and E. H-Mean Sha, "Rotation Scheduling: A Loop Pipelining Algorithm", IEEE transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 3, March 1997.
5. K.S. Chatha and R. Vemuri, "RECOD: A Retiming Heuristic to Optimize Resource and Memory Utilization in HW/SW Code- signs, " Proceedings of Sixth International Workshop on Hardware/Software Codesign, Seattle, March 1998.
6. K.S. Chatha and R. Vemuri, "Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns, " Proceedings of Nineth IEEE International Workshop on Rapid System Prototyping, Leuven, Belgium, June 1998.
7. R. Ernst, J. Henkel and T. Benner, "Hardware-software cosynthe- sis for microcontrollers, " IEEE Design and Test of Computers, pp 64-75, 1994.
8. B. Fluiter, E.H.L. Aarts, J.H.M. Korst, W.F.J. Verhaegh and A.V.D. Werf, "The complexity of Generalised Retiming Problem", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 11, November 1996.
9. R. Gupta and G.D. Micheli "Hardware-software cosynthesis for digital systems, " IEEE Design and Test of Computers, vol 10, no. 3, pp 29-41, 1993.
10. A. Kalavade and E.A. Lee, "The Extended Partitioning Problem: Hardware/Software Mapping, Scheduling and Implementation-Bin Selection", Journal of Design Automation for Embedded Systems, Kluwer, Vol. 2, No. 2, pp. 125-163, 1997.
11. E.A. Lee and D.G. Messerschmitt, "Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing", IEEE Transactions on Computers, Vol C-36, No 1, January 1987.
12. C. E. Leiserson and J. B. Saxe, "Retiming Synchronous Circuitry", Algorithmica, vol. 6, no. 1, pp. 5-35, 1991.
13. R. Niemann and P. Marwedel, "Hardware/Software Partitioning using Integer Programming, " Proceedings of ED & TC, 1996.
14. K.K. Parhi and D.G. Messershmitt, "Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding, " IEEE Transactions on Computers, 178-195, 1991.
15. F. Sanchez, Loop Pipelining With Resource And Timing Constraints, Ph.D. Dissertation, UPC Universitat Politfechnica de Catalunya, Barcelona, Spain, October 1995.