Implementing multi-VRC cores to evolve combinational logic circuits in parallel

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4684 LNCS, Issue , 2007, Pages 23-34

  Wang, Jin ^a   Piao, Chang Hao ^b   Lee, Chong Ho ^a  

^a Inha University   (South Korea)

^b CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS   (China)

Author keywords

Incremental evolution; Intrinsic evolvable hardware; Parallel evolutionary algorithm; Scalability

Indexed keywords

COMPUTATIONAL EFFICIENCY; COMPUTER HARDWARE; EVOLUTIONARY ALGORITHMS; PARALLEL ALGORITHMS; SCALABILITY; VIRTUAL REALITY;

INCREMENTAL EVOLUTION; INTRINSIC EVOLVABLE HARDWARE; PARALLEL EVOLUTIONARY ALGORITHMS;

LOGIC CIRCUITS;

EID: 38049082637     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-74626-3_3     Document Type: Conference Paper

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