A flexible general-purpose parallelizing architecture for nested loops in reconfigurable platforms

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4644 LNCS, Issue , 2007, Pages 20-30

  Panagopoulos, Ioannis ^a   Pavlatos, Christos ^a   Manis, George ^b   Papakonstantinou, George ^a  

^a NATIONAL TECHNICAL UNIVERSITY OF ATHENS   (Greece)

^b UNIVERSITY OF IOANNINA   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL OPTIMIZATION; COMPUTER HARDWARE; DYNAMIC MODELS; IMAGE PROCESSING; MEMORY ARCHITECTURE; SCHEDULING; SYSTEMS ANALYSIS;

FINE GRAIN PARALLELISM; GENERAL PURPOSE ARCHITECTURES; HARDWARE IMPLEMENTATIONS; LOAD BALANCING TECHNIQUE; PERFORMANCE ESTIMATION; PROCESSING ELEMENTS; PROPOSED ARCHITECTURES; RECONFIGURABLE PLAT-FORMS;

RECONFIGURABLE ARCHITECTURES;

EID: 37849041700     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-74442-9_3     Document Type: Conference Paper

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