High level synthesis of degradable ASICs using virtual binding

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2007, Pages 311-317

  Honarmand, N ^a   Shahabi, A ^a   Sohofi, H ^a   Abbaspour, M ^b   Navabi, Z ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

^b SHAHID BEHESHTI UNIVERSITY   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONFORMAL MAPPING; DEGRADATION; MULTIPLEXING; VIRTUAL REALITY;

DEGRADED PERFORMANCE; HIGH LEVEL SYNTHESIS; VIRTUAL BINDING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 37549016430     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2007.36     Document Type: Conference Paper

References (11)

1. L.M. Guerra, M.M. Potkonjak, and J.M. Rabaey, "High-Level Synthesis Techniques For Efficient Built-In-Self-Repair", The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993, pp. 41-48.
2. L.M. Guerra, M. Potkonjak, and J.M. Rabaey, "Behavioral-Level Synthesis of Heterogeneous BISR Reconfigurable ASIC's," IEEE Transactions on VLSI Systems, vol. 6, no. 1, pp. 158-167, Mar. 1998.
3. R. Naidu, and S. Mahapatra, "Fault Tolerance in N-MOS Random Access Memories with Dynamic Redundancy Methods", Microelectronics and Reliability, vol. 28, no. 2, pp. 193-200, 1988.
4. R. Negrini, M.G. Sami, and R. Stefanelli, "Fault Tolerance Through Reconfiguration in VLSI and WSI Arrays", MIT Press, 1989.
5. G. De Micheli, "Synthesis and Optimization of Digital Circuits", McGraw-Hill, Hightstown, NJ, 1994.
6. G. Buonanno, M. Pugassi, and M.G. Sami, "A high-level synthesis approach to design of fault-tolerant systems" in Proc. VTS'97, pp. 356-361, 1997.
7. B. Iyer, R. Karri, and I. Koren. "Phantom Redundancy: A High-Level Synthesis Approach for Manufacturability", In Proc. ICCAD, pp. s-661, Nov. 1995.
8. Wah Chan, and A. Orailoglu, "High-level synthesis of gracefully degradable ASICs," in Proc. ED&TC, pp. 50-54, 1996.
9. A. Orailoglu, "Microarchitectural Synthesis of Gracefully Degradable, Dynamically Reconfigurable ASICs," in Proc. of ICCD'96, pp.112-117, Oct. 1996.
10. S. Mitra, W.-J Huang, N.R. Saxena, S.-Y. Yu, and E.J. McCluskey, "Reconfigurable Architecture For Autonomous Self-Repair", IEEE Design & Test of Computers, vol. 21, no. 3, pp. 228- 240, May-Jun. 2004.
11. P. Paulin and J. Knight, "Force-Directed Scheduling for the Behavioral Synthesis of ASICs", IEEE Transactions on CAD/ICAS, Vol. CAD-8, No. 6, pp. 661-679, July 1989.