Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1996, Pages 112-117

  Orailoglu, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; ELECTRIC NETWORK SYNTHESIS; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUIT TESTING; OPTIMIZATION;

BAND RECONFIGURATION; HARDWARE UTILIZATION; MULTIPLE PERMANENT FAULTS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0030421688     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)