High-level synthesis of gracefully degradable ASICs

Proceedings of European Design and Test Conference

Volumn , Issue , 1996, Pages 50-54

  Chan, Wah ^a   Orailoglu, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUIT LAYOUT;

GRACEFUL DEGRADATION SCHEME; HIGH LEVEL SYNTHESIS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0029734626     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)