Checkpointing alternatives for high-performance, power-aware processors

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 318-321

  Moshovos, A ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

Algorithm design and analysis; Checkpointing; Maintenance; Out of order; Permission; Power dissipation; Power generation; Processor scheduling; Registers; Temperature

Indexed keywords

ENERGY DISSIPATION; LOW POWER ELECTRONICS; MAINTENANCE; POWER ELECTRONICS; POWER GENERATION; RATS; TEMPERATURE;

ALGORITHM DESIGN AND ANALYSIS; CHECK POINTING; OUT OF ORDER; PERMISSION; PROCESSOR SCHEDULING; REGISTERS;

POWER MANAGEMENT;

EID: 1542359133     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231886     Document Type: Conference Paper

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