A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2007, Pages 8-13

  Joshi, Rajiv ^a   Kanj, Rouwaida ^b   Kim, Keunwoo ^a   Williams, Richard ^c   Chuang, Ching Te ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

^c IBM   (United States)

Author keywords

Booster circuit; Low power; SRAM; Yield

Indexed keywords

BOOSTER CIRCUIT; DYNAMIC SUPPLY; LOW POWER;

CIRCUIT THEORY; COMPUTER SIMULATION; ELECTRIC POTENTIAL; MONTE CARLO METHODS; SILICON ON INSULATOR TECHNOLOGY; STATIC RANDOM ACCESS STORAGE;

CMOS INTEGRATED CIRCUITS;

EID: 36949009622     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1283780.1283784     Document Type: Conference Paper

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