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Volumn , Issue , 2007, Pages 190-199

Reverse state reconstruction for sampled microarchitectural simulation

Author keywords

[No Author keywords available]

Indexed keywords

MICROARCHITECTURAL SIMULATION; PROCESSOR SIMULATION TIMES; REVERSE STATE RECONSTRUCTION;

EID: 36949004093     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2007.363749     Document Type: Conference Paper
Times cited : (6)

References (20)
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  • 2
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    • Combining Trace Sampling With Single Pass Methods for Efficient Cache Simulation
    • Jun
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  • 3
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    • PhD thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana, Illinois
    • Conte, T. M. Systematic computer architecture prototyping. PhD thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana, Illinois, 1992.
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    • Conte, T.M.1
  • 4
    • 0030402384 scopus 로고    scopus 로고
    • Conte, T. M., Hirsch, M. A., and Menezes, K. N. Reducing State Loss for Effective Trace Sampling of Superscalar Processors. In Proc of the 1996 International Conference on Computer Design, (Austin, TX), Oct. 1996.
    • Conte, T. M., Hirsch, M. A., and Menezes, K. N. Reducing State Loss for Effective Trace Sampling of Superscalar Processors. In Proc of the 1996 International Conference on Computer Design, (Austin, TX), Oct. 1996.
  • 5
    • 25844526328 scopus 로고    scopus 로고
    • BLRL: Accurate and Efficient Warmup for Sampled Processor Simulation
    • Oxford University Press
    • EeckHout, L., Luo, Y., Bosschere, K. D., and John, L. K. BLRL: Accurate and Efficient Warmup for Sampled Processor Simulation. The Computer Journal, 2005 Oxford University Press. Vol. 48 (4). 2005. pp. 451-459.
    • (2005) The Computer Journal, 2005 , vol.48 , Issue.4 , pp. 451-459
    • EeckHout, L.1    Luo, Y.2    Bosschere, K.D.3    John, L.K.4
  • 6
    • 0028013968 scopus 로고    scopus 로고
    • Fu, J. W. C., and Patel, J. H. Trace driven simulation using sampled traces. In Proc. 27th Hawaii Int'l. Conf. on System Sciences, (Maui, HI), Jan. 1994.
    • Fu, J. W. C., and Patel, J. H. Trace driven simulation using sampled traces. In Proc. 27th Hawaii Int'l. Conf. on System Sciences, (Maui, HI), Jan. 1994.
  • 7
    • 84943402809 scopus 로고    scopus 로고
    • Haskins, J. W., and Skadron, K. Memory Reference Reuse Latency: Accelerated Sampled Microarchitecture Simulation. In Proc of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, pp. 195-203, Mar. 2003.
    • Haskins, J. W., and Skadron, K. Memory Reference Reuse Latency: Accelerated Sampled Microarchitecture Simulation. In Proc of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, pp. 195-203, Mar. 2003.
  • 8
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    • Newbury Park, CA: Sage Publications
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  • 9
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    • A comparison of trace-sampling techniques for multi-megabyte caches
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    • (1994) IEEE Trans. Comput , vol.C-43 , pp. 664-675
    • Kessler, R.E.1    Hill, M.D.2    Wood, D.A.3
  • 10
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    • Accurate low-cost methods for performance evaluation of cache memory systems
    • Feb
    • Laha, S., Patel, J. A., and Iyer, R. K. Accurate low-cost methods for performance evaluation of cache memory systems. IEEE Trans. Comput, vol. C-37, pp. 1325-1336, Feb. 1988.
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  • 11
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.