Flexible signal processing platform chip for software defined radio with 103 GOPS dynamic reconfigurable logic cores

2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006

Volumn , Issue , 2006, Pages 67-70

  Fujisawa, Hisanori ^a   Saito, Miyoshi ^a   Nishijima, Seiichi ^a   Odate, Naoki ^a   Sakai, Yuki ^a   Yoda, Katsuhiro ^a   Sugiyama, Iwao ^a   Ishihara, Teruo ^a   Hirose, Yoshio ^a   Yoshizawa, Hideki ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; LSI CIRCUITS; SIGNAL PROCESSING; WIRELESS TELECOMMUNICATION SYSTEMS;

LOGIC CORES; SHORT LATENCY HARDWARE; SOFTWARE DEFINED RADIO;

MICROPROCESSOR CHIPS;

EID: 34250865688     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2006.357853     Document Type: Conference Paper

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