Low electrical resistance silicon through vias: Technology and characterization

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 1360-1366

  Henry, D ^a   Belhachemi, D ^a   Souriau, J C ^a   Brunet Manquat, C ^a   Puget, C ^a   Ponthenier, G ^a   Vallejo, J L ^a   Lecouvey, C ^a   Sillon, N ^a  

^a CEA GRENOBLE   (France)

Author keywords

Conformity; Heterogeneous integration; Silicon through vias; System on wafer (SoW)

Indexed keywords

CHIP SCALE PACKAGES; ELECTRIC INSULATION; ELECTRIC RESISTANCE; ELECTRONICS PACKAGING; RELIABILITY THEORY;

CONFORMITY; HETEROGENEOUS INTEGRATION; INTERCONNECTION DENSITY; SILICON THROUGH VIAS (STV); SYSTEM ON WAFER (SOW);

SEMICONDUCTING SILICON;

EID: 33845570490     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645834     Document Type: Conference Paper

References (9)

1. Rao R. Tummala et al - "High density packaging in 2010 and beyond" - 2002 International Symposium on Electronic Materials and packaging - IEEE - pp 30-36.
2. N. Sillon et al - "Innovative flip chip solution for System on Wafer concept" - 3S workshop - September 2005 - Atlanta.
3. JC Souriau et al - "Wafer Level Processing Of 3D System In Package For RF And Data Applications" - Electronic Components and Technology Conference, May 31 - June 3, 2005, Orlando, Florida
4. Rao R. Tummala - "SOP: What is it and why? A new Microsystems-Integration Technology Paradigm-Moore's Law for system integration of miniaturized convergent systems of the next decade" - IEEE Transactions On advanced Packaging - Vol 27, No 2, may 2004 - pp 241-249
5. K. Takahashi et al - "Process integration of 3D Chip stack with vertical interconnection" - 54th Electronic Components and Technology Conf, Las Vegas, Nevada, May 2004-pp 601-609.
6. M Umemoto et al - "High-Performance Vertical Interconnection for high density 3D Chip Stacking Package" 54th Electronic Components and Technology Conf, Las Vegas, Nevada, May 2004, pp.616-623.
7. D. Henry - C. Gillot - N. Sillon - "Through vias technology for System on wafer approach" - ENCAST Workshop Zurich - 08 & 09 november 2005.
8. JC. Souriau - Final report of WALPACK Project - European PIDEA contact No GR 773 430/2 - May 2005.
9. D. Henry et al - "Post-process silicon through vias technology with low electrical resistance" - IWLPC 2005 - San José November 2005.