SPICE compatible modelling of on-chip coupled interconnects

Electronics Letters

Volumn 43, Issue 24, 2007, Pages 1336-1338

  Kumar, R ^a   Kang, K ^a   Rustagi, S C ^a   Mouthaan, K ^b   Wong, T K S ^c  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COPPER; MICROPROCESSOR CHIPS; PARAMETER ESTIMATION; SPICE; TIME DOMAIN ANALYSIS;

COUPLED LINE MODEL PARAMETERS; ON-CHIP COUPLED INTERCONNECTS;

INTEGRATED CIRCUITS;

EID: 36448997062     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20072620     Document Type: Article

References (7)

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2. Maffezzoni, P., and Brambilla, A.: ' Modelling delay and crosstalk in VLSl interconnect for electrical simulation ', Electron. Lett., 2000, 36, (10), p. 862-864 0013-5194
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7. Cheng-Nan, C.: ' Closed-form expressions for the line-coupling parameters of coupled on-chip interconnects on lossy silicon substrate ', Microw. Opt. Technol. Lett., 2004, 43, (6), p. 495-498 0895-2477