The effect of board sffifness on the solder-joint reliability of HVQFN-packages

EuroSime 2007: International Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems, 2007

Volumn , Issue , 2007, Pages

  De Vries, J ^a   Jansen, M ^a   Van Driel, W ^b,c  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

^c DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRONICS PACKAGING; INTERCONNECTION NETWORKS; PHYSICAL PROPERTIES; SOLDERED JOINTS; THERMAL CYCLING; THERMAL EXPANSION;

PANEL THICKNESS; SOLDERED INTERCONNECTIONS; TEST LOADS;

PRINTED CIRCUIT BOARDS;

EID: 36348950297     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESIME.2007.360021     Document Type: Conference Paper

References (12)

1. Hung, S.C., Zheng, PX, Ho, S.H., Lee, S.C., Wu. J.D., "The comparison of solder joint reliability between BCC++ and QFN," Proc. Electronic Components and Technology Conf, 2001. pp. 1052-1058.
2. Syed, A., Kang, W.J., "Board level assembly and reliability considerations for QFN type packages," Proc. Surface Mount Technology Association, 2003, pp. 181-188.
3. Tee, T.Y., Ng, H.S., Yap, D., Zhong, Z., "Comprehensive board-level solder joint reliability modeling and testing of QFN and power QFN packages," Microelectronics Reliability, vol. 43 (2003), pp. 1329-1338.
4. Mercado, LX., Sarihan, V., Fiorenzo, R., "A performance and manufacturability evaluation of bump chip carrier packages,". IEEE Trans. Adv. Pack, Vol. 27 (2004), pp. 151-157.
5. Stoeckl, S., Pape, H. "Improving the solder joint reliability of VQFN-packages," Proc Electronics Packaging Technology Conf, 2005, pp. 760-767.
6. Qi, H., Ganesan, S., Wu, J., Pecht, M., "Effects of printed circuit board materials on lead-free interconnect durability," Proc. Int. Conf On Polymers and Adhesives in Microelectronics and Photonics, 2005, pp. 140-144.
7. Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments, IPC9701, 2006.
8. Engelmaier, W., "Fatigue life of leadless chip carrier solder joints during power cycling," IEEE Trans. Comp. Hybrids & Manuf. Techn., Vol. 6 (1983), pp. 232-237.
9. Osterman, M., "Effect of temperature cycle on the durability of lead free interconnects (Sn-Ag-Cu and Sn-Ag)," CalceEPSC project C05-06, 2005.
10. Darveaux, R., Banerjee, K., "Constitutive relations for Tin-based solder joints," IEEE Trans. Comp. Hybrids & Manuf. Techn., vol. 15 (1992), pp. 1013-1024.
11. Schubert, A., Dudek, R., Doering, R., Walter, H., Auerswald, E., Gollhardt, A., Schuch, B., Sitzmann, H., Michel, B., "Lead-free solder interconnects: characterization, testing, reliability," Proc. EuroSimE, 2002, pp. 62-73.
12. Wiese, S., Schubert, A., Walter, H., Dudek, R., Feustel, F., Meusel, E., Michel, B., "Constitutive behavior of Lead-free solders vs. Lead-containing solders - experiments on bulk specimens and flip-chip joints," Proc. Electronic Components and Technology Conf, 2001, pp. 890-903.