-
1
-
-
0842309728
-
-
M. Lundstrom, Device physics at the scaling limit: What matters? in IEDM Tech. Dig., 33.1.1-33.1.4, Dec. 2003.
-
M. Lundstrom, "Device physics at the scaling limit: What matters?" in IEDM Tech. Dig., 33.1.1-33.1.4, Dec. 2003.
-
-
-
-
2
-
-
3042725097
-
Reverse-order source drain formation with double offset spacer (RODOS) for low-power and high-speed application
-
Dec
-
W. Y. Choi, B. Y. Choi, D.-S. Woo, J. D. Lee, and B.-G. Park, "Reverse-order source drain formation with double offset spacer (RODOS) for low-power and high-speed application," IEEE Trans. Nanotechnol. vol. 2, no. 4, pp. 210-216, Dec. 2003.
-
(2003)
IEEE Trans. Nanotechnol
, vol.2
, Issue.4
, pp. 210-216
-
-
Choi, W.Y.1
Choi, B.Y.2
Woo, D.-S.3
Lee, J.D.4
Park, B.-G.5
-
4
-
-
0033098648
-
Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates
-
Mar
-
J. E Chen, J. Tao, P. Fang, and C. Hu, "Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates," IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 367-371, Mar. 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.3
, pp. 367-371
-
-
Chen, J.E.1
Tao, J.2
Fang, P.3
Hu, C.4
-
5
-
-
0024870094
-
Asymmetric halo source GOLD drain (HS-GOLD) deep sub-half micron n-MOSFET design for reliability and performance
-
Dec
-
T. N. Buti, S. Ogura, N. Rovedo, K. Tobimatsu, and C. F. Codella, "Asymmetric halo source GOLD drain (HS-GOLD) deep sub-half micron n-MOSFET design for reliability and performance," in IEDM Tech. Dig. Dec. 1989, pp. 617-620.
-
(1989)
IEDM Tech. Dig
, pp. 617-620
-
-
Buti, T.N.1
Ogura, S.2
Rovedo, N.3
Tobimatsu, K.4
Codella, C.F.5
-
6
-
-
0028380786
-
An asymmetric sidewall process for high performance LDD MOSFET
-
Feb
-
T. Horiuchi, T. Homma, Y. Murao, and K. Okumura, "An asymmetric sidewall process for high performance LDD MOSFET," IEEE Trans. Electron Devices, vol. 41, no. 2, pp. 186-190, Feb. 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, Issue.2
, pp. 186-190
-
-
Horiuchi, T.1
Homma, T.2
Murao, Y.3
Okumura, K.4
-
7
-
-
0033259934
-
Realization of ultrafine lines using sidewall structures and their application to nMOSFETs
-
Dec
-
S.-K. Sung, Y. J. Choi, J. D. Lee, and B.-G. Park, "Realization of ultrafine lines using sidewall structures and their application to nMOSFETs," J. Korean Phys. Soc., vol. 35, pp. S693-696, Dec. 1999.
-
(1999)
J. Korean Phys. Soc
, vol.35
-
-
Sung, S.-K.1
Choi, Y.J.2
Lee, J.D.3
Park, B.-G.4
-
8
-
-
0036002414
-
Nanoscale-wire patterning using side-wall and quantum dot memory device fabrication
-
Jan
-
S.-K. Sung, J. S. Sim, D. H. Kim, J. D. Lee, and B.-G. Park, "Nanoscale-wire patterning using side-wall and quantum dot memory device fabrication," J. Korean Phys. Soc., vol. 40, no. 1, pp. 128-131, Jan. 2002.
-
(2002)
J. Korean Phys. Soc
, vol.40
, Issue.1
, pp. 128-131
-
-
Sung, S.-K.1
Sim, J.S.2
Kim, D.H.3
Lee, J.D.4
Park, B.-G.5
-
9
-
-
0035803208
-
Single-electron transistor based on silicon-on-insulator quantum wire fabricated by a side-wall patterning method
-
Dec
-
D. H. Kim, S.-K. Sung, J. S. Sim, K. R. Kim, J. D. Lee, B.-G. Park, B. H. Choi, S. W. Hwang, and D. Ahn, "Single-electron transistor based on silicon-on-insulator quantum wire fabricated by a side-wall patterning method," Appl. Phys. Lett., vol. 79, no. 23, pp. 3812-3814, Dec. 2001.
-
(2001)
Appl. Phys. Lett
, vol.79
, Issue.23
, pp. 3812-3814
-
-
Kim, D.H.1
Sung, S.-K.2
Sim, J.S.3
Kim, K.R.4
Lee, J.D.5
Park, B.-G.6
Choi, B.H.7
Hwang, S.W.8
Ahn, D.9
-
10
-
-
0035981421
-
Fabrication of a 30-nm planar nMOSFETs based on the sidewall patterning technique
-
Oct
-
W. Y. Choi, B. Y. Choi, Y. J. Choi, D.-S. Woo, S.-K. Sung, J. D. Lee, and B.-G. Park, "Fabrication of a 30-nm planar nMOSFETs based on the sidewall patterning technique," J. Korean Phys. Soc., vol. 41, no. 4, pp. 497-500, Oct. 2002.
-
(2002)
J. Korean Phys. Soc
, vol.41
, Issue.4
, pp. 497-500
-
-
Choi, W.Y.1
Choi, B.Y.2
Choi, Y.J.3
Woo, D.-S.4
Sung, S.-K.5
Lee, J.D.6
Park, B.-G.7
|