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Volumn 54, Issue 11, 2007, Pages 2969-2974

Design and fabrication of asymmetric MOSFETs using a novel self-aligned structure

Author keywords

Asymmetric MOSFET; Lightly doped drain (LDD); Mesa structure; Sidewall spacer gate

Indexed keywords

DRAIN CURRENT; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 36248982072     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.906969     Document Type: Article
Times cited : (16)

References (10)
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    • T. Horiuchi, T. Homma, Y. Murao, and K. Okumura, "An asymmetric sidewall process for high performance LDD MOSFET," IEEE Trans. Electron Devices, vol. 41, no. 2, pp. 186-190, Feb. 1994.
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  • 7
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    • Realization of ultrafine lines using sidewall structures and their application to nMOSFETs
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    • S.-K. Sung, Y. J. Choi, J. D. Lee, and B.-G. Park, "Realization of ultrafine lines using sidewall structures and their application to nMOSFETs," J. Korean Phys. Soc., vol. 35, pp. S693-696, Dec. 1999.
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    • S.-K. Sung, J. S. Sim, D. H. Kim, J. D. Lee, and B.-G. Park, "Nanoscale-wire patterning using side-wall and quantum dot memory device fabrication," J. Korean Phys. Soc., vol. 40, no. 1, pp. 128-131, Jan. 2002.
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    • D. H. Kim, S.-K. Sung, J. S. Sim, K. R. Kim, J. D. Lee, B.-G. Park, B. H. Choi, S. W. Hwang, and D. Ahn, "Single-electron transistor based on silicon-on-insulator quantum wire fabricated by a side-wall patterning method," Appl. Phys. Lett., vol. 79, no. 23, pp. 3812-3814, Dec. 2001.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.