Return of the hardware floating-point elementary function

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 2007, Pages 161-168

  Detrey, Jérémie ^a   De Dinechin, Florent ^a   Pujol, Xavier ^a  

^a UNIVERSITÉ DE LYON   (France)

Author keywords

Exponential; Floating point elementary functions; FPGA; Hardware operator; Logarithm

Indexed keywords

COMPUTER HARDWARE; COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUNCTION EVALUATION; SILICON;

FLOATING-POINT ELEMENTARY FUNCTIONS; HARDWARE OPERATOR; LOGARITHM FUNCTIONS; SOFTWARE FUNCTIONS;

DIGITAL ARITHMETIC;

EID: 36048979064     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARITH.2007.29     Document Type: Conference Paper

References (26)

1. C. S. Anderson, S. Story, and N. Astafiev. Accurate math functions on the intel IA-32 architecture: A performancedriven design. In 7th Conference on Real Numbers and Computers, pages 93-105, 2006.
2. ANSI/IEEE. Standard 754-1985 for Binary Floating-Point Arithmetic (also IEC 60559). 1985.
3. M. Cornea, J. Harrison, and P. Tang. Scientific Computing on Itanium-based Systems. Intel Press, 2002.
4. M. Cosnard, A. Guyot, B. Hochet, J. M. Muller, H. Ouaouicha, P. Paul, and E. Zysmann. The FELIN arithmetic coprocessor chip. In Eighth IEEE Symposium on Computer Arithmetic, pages 107-112, 1987.
5. M. deLorimier and A. DeHon. Floating-point sparse matrix-vector multiply for FPGAs. In ACM/SIGDA FieldProgrammable Gate Arrays, pages 75-85. ACM Press, 2005.
6. J. Detrey and F. de Dinechin. A parameterizable floatingpoint logarithm operator for FPGAs. In 39th Asilomar Conference on Signals, Systems & Computers. IEEE Signal Processing Society, Nov. 2005.
7. J. Detrey and F. de Dinechin. A parameterized floating-point exponential function for FPGAs. In IEEE International Conference on Field-Programmable Technology (FPT'05). IEEE Computer Society Press, Dec. 2005.
8. J. Detrey and F. de Dinechin. Table-based polynomials for fast hardware function evaluation. In 16th Intl Conference on Application-specific Systems, Architectures and Processors. IEEE Computer Society Press, July 2005.
9. Y Dou, S. Vassiliadis, G. K. Kuzmanov, and G. N. Gaydadjiev. 64-bit floating-point FPGA matrix multiplication. In ACM/SIGDA Field-Programmable Gate Arrays. ACM Press, 2005.
10. M. Ercegovac. Radix-16 evaluation of certain elementary functions. IEEE Transactions on Computers, C-22(6):561-566, June 1973.
11. M. D. Ercegovac and T. Lang. Digital Arithmetic. Morgan Kaufmann, 2003.
12. P. Farmwald. High-bandwidth evaluation of elementary functions. In Fifth IEEE Symposium on Computer Arithmetic, pages 139-142, 1981.
13. H. Hassler and N. Takagi. Function evaluation by table lookup and addition. In 12th IEEE Symposium on Computer Arithmetic, pages 10-16, Bath, UK, 1995. IEEE.
14. ISO/IEC. International Standard ISO/IEC 9899:1999(E). Programming languages-C. 1999.
15. D. Lee, A. Gaffar, O. Mencer, and W. Luk. Optimizing hardware function evaluation. IEEE Transactions on Computers, 54(12):1520-1531, Dec. 2005.
16. G. Lienhart, A. Kugel, and R. Männer. Using floating-point arithmetic on FPGAs to accelerate scientific N-body simulations. In FPGAs for Custom Computing Machines. IEEE, 2002.
17. J.-M. Müller. Elementary Functions, Algorithms and Implementation. Birkhäuser, 2 edition, 2006.
18. G. Paul and M. W Wilson. Should the elementary functions be incorporated into computer instruction sets? ACM Transactions on Mathematical Software, 2(2): 132-142, June 1976.
19. J. Stine and M. Schulte. The symmetric table addition method for accurate function approximation. Journal of VLSI Signal Processing, 21 (2): 167-177, 1999.
20. P. T. P. Tang. Table-driven implementation of the exponential function in IEEE floating-point arithmetic. ACM Transactions on Mathematical Software, 15(2):144-157, June 1989.
21. P. T. P. Tang. Table-driven implementation of the logarithm function in IEEE floating-point arithmetic. ACM Transactions on Mathematical Software, 16(4):378 - 400, Dec. 1990.
22. K. Underwood. FPGAs vs. CPUs: Trends in peak floatingpoint performance. In ACM/SIGDA Field-Programmable Gate Arrays. ACM Press, 2004.
23. W. F. Wong and E. Goto. Fast evaluation of the elementary functions in double precision. In Twenty-Seventh Annual Hawaii International Conference on System Sciences, pages 349-358, 1994.
24. W. F. Wong and E. Goto. Fast hardware-based algorithms for elementary function computations using rectangular multipliers. IEEE Transactions on Computers, 43(3):278-294, Mar. 1994.
25. W. F. Wong and E. Goto. Fast evaluation of the elementary functions in single precision. IEEE Transactions on Computers, 44(3):453-457, Mar. 1995.
26. C. Wrathall and T. C. Chen. Convergence guarantee and improvements for a hardware exponential and logarithm evaluation scheme. In Fourth IEEE Symposium on Computer Arithmetic, pages 175-182, 1978.