Systematic layout planning: A study on semiconductor wafer fabrication facilities

International Journal of Operations and Production Management

Volumn 20, Issue 11, 2000, Pages 1359-1371

  Yang, Taho ^a   Su, Chao Ton ^b   Hsu, Yuan Ru ^b  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Analytical hierarchy process; Decision making; Layout; Material handling; Semiconductors

Indexed keywords

EID: 3543092650     PISSN: 01443577     EISSN: None     Source Type: Journal    
DOI: 10.1108/01443570010348299     Document Type: Article

References (14)

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