Alternative facility layouts for semiconductor wafer fabrication facilities

IEEE transactions on components, packaging and manufacturing technology. Part C. Manufacturing

Volumn 20, Issue 2, 1997, Pages 152-163

  Geiger, Christopher D ^a   Hase, Rieko ^a   Takoudis, Christos G ^a   Uzsoy, Reha ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSEMBLY MACHINES; CMOS INTEGRATED CIRCUITS; PLANT LAYOUT; PROCESS CONTROL; RELIABILITY;

SEMICONDUCTOR WAFER FABRICATION FACILITIES;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0031119940     PISSN: 10834400     EISSN: None     Source Type: Journal    
DOI: 10.1109/3476.622885     Document Type: Article

References (33)

1. E. Akcali K. Nemoto R. Uzsoy Cycle time improvements for photolithography processes in semiconductor manufacturing 1996 School Ind. Eng., Purdue Univ. IN, West Lafayette Res. Rep.
2. C. L. Ang P. C. T. Willey A comparative study of the performance of pure and hybrid group technology manufacturing systems using computer simulation techniques Int. J. Prod. Res. 22 193 233 1984
3. W. Barnett R. K. Schneider Impact of minienvironments on facilities cost Proc. Int. Electron. Manufact. Technol. Symp. 286 291 1995 TX, Austin 4023 11545 526128
4. J. L. Burbidge Production Flow Analysis. 1989 Oxford New York
5. P. Castrucci Design of future single-wafer logic fabs Proc. Int. Electron. Manufact. Technol. Symp. 283 285 1995 TX, Austin 4023 11545 526127
6. S. Chen R. Hase K. Mordaunt R. Uzsoy C. G. Takoudis Relationships between process fundamentals, facility design and production control of semiconductor manufacturing facilities Proc. Microelectron. Manufact. '95 Oct. 1995 TX, Austin
7. L. M. Wein On the relationship between yield and cycle time in semiconductor wafer fabrication IEEE Trans. Semiconduct. Manufact. 5 156 158 1992 66 3715 136277
8. S. C. Wood Adaptable Manufacturing Systems for Semiconductor Integrated Circuit Production 1994 Ph.D. dissertation CA, Stanford
9. S. P. Cunningham J. G. Shanthikumar Empirical results on the relationship between die yield and cycle time in semiconductor wafer fabrication IEEE Trans. Semiconduct. Manufact. 9 273 277 1996 66 10608 492822
10. B. B. Flynn F. R. Jacobs A simulation comparison of group technology with traditional job shop manufacturing Int. J. Prod. Res. 24 1171 1192 1986
11. B. B. Flynn F. R. Jacobs An experimental comparison of cellular (group technology) layout with process layout Decision Sci. 18 562 581 1987
12. J. A. Friedrich G. W. Neudeck Three dimensional MOS process development IEEE Electron Device Lett. 10 144 1989 55 1377 31698
13. C. R. Glassey M. G. C. Resende Closed-loop job release control for VLSI circuit manufacturing IEEE Trans. Semiconduct. Manufact. 1 36 46 1988 66 240 4371
14. E. M. Goldratt J. Cox The Goal: A Process of Ongoing Improvement. 1986 North River U.K., London
15. E. M. Goldratt R. E. Fox The Race 1986 North River U.K., London
16. T. J. Greene R. P. Sadowski A review of cellular manufacturing assumptions, advantages and design techniques J. Oper. Manag. 4 85 97 1984
17. R. Guo M. Slama R. Griffin K. Holman A work cell manufacturing system for VLSI fabrication Proc. IEEE/CHMT Int. Electron. Manufact. Technol. Symp. 200 205 1993 3174 8999 398202
18. R. C. Hase Reentrant and Cellular Layouts for Semiconductor Wafer Fabrication Facilities 1995 M.S. thesis IN, West Lafayette
19. R. C. Hase C. G. Takoudis R. Uzsoy Cellular and reentrant layouts for wafer fabrication Proc. Electrochem. Soc. Meet. 1994 CA, San Francisco
20. D. Kayton T. Teyner C. Schwartz R. Uzsoy Effects of dispatching and down time on the performance of wafer fabs operating under theory of constraints Proc. Int. Electron. Manufact. Technol. Symp. Oct. 1996 TX, Austin 4092 12200 559681
21. A. Law W. D. Kelton Simulation Modeling and Analysis 2nd 1991 McGraw-Hill New York
22. S. R. Lawrence A. H. Buss Shifting production bottlenecks: Causes, cures and conundrums Prod. Oper. Manag. 3 21 37 1994
23. S. H. Lu P. R. Kumar Distributed scheduling based on due dates and buffer priorities IEEE Trans. Automat. Contr. 36 1406 1416 1991 9 3244 106156
24. C. L. Moodie R. Uzsoy Y. Yih Cellular Manufacturing: A Systems Engineering Approach 1995 Taylor and Francis U.K., London
25. K. Nemoto E. Akcali R. Uzsoy Quantifying the benefits of cycle time reduction in semiconductor wafer fabrication Proc. Int. Electron. Manufact. Technol. Symp. 1996 TX, Austin
26. O. G. Okogbaa M. Chen C. Changchit R. L. Shell Manufacturing system cell formation and evaluation using a new inter-cell flow reduction heuristic Int. J. Prod. Res. 30 1101 1118 1992
27. I. M. Ovacik R. Uzsoy Decomposition Methods for Complex Factory Scheduling Problems. 1997 Kluwer MA, Norwell
28. A. A. B. Pritsker Introduction to Simulation and SLAMII. 1986 Systems IN, West Lafayette
29. H. J. Steudel P. Desruelle Manufacturing in the Nineties. 1992 Van Nostrand Reinhold New York
30. D. R. Sule Manufacturing Facilities: Location, Planning and Design. 1988 PWS-Kent MA, Boston
31. R. Uzsoy C. Y. Lee L. A. Martin-Vega A review of production planning and scheduling models in the semiconductor industry Part I: System characteristics, performance evaluation and production planning IIE Trans. Scheduling Logistics 24 47 61 1992
32. R. Uzsoy C. Y. Lee L. A. Martin-Vega A review of production planning and scheduling models in the semiconductor industry Part II: Shop-floor control IIE Trans. Scheduling Logistics 26 44 55 1994
33. L. M. Wein Scheduling semiconductor wafer fabrication IEEE Trans. Semiconduct. Manufact. 1 3 115 129 1988 66 242 4384