Incorporating manufacturing objectives into the semiconductor facility layout design process: a methodology and selected cases

IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop

Volumn , Issue , 1997, Pages 434-439

  Padillo, Jose M ^a   Meyersdorf, Doron ^a   Reshef, Offer ^a  

^a TEFEN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECISION MAKING; INTERFACES (COMPUTER); PERFORMANCE; PRODUCT DESIGN; SEMICONDUCTOR DEVICE STRUCTURES;

ANALYTICAL HIERARCHY PROCESS; DECISION MATRIX; SEMICONDUCTOR FACILITY LAYOUT DESIGN PROCESSES;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0031340904     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)