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Volumn 32, Issue 1, 2003, Pages 51-62

Statistical yield modeling for IC manufacture: Hierarchical fault distributions

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; ELECTRIC FAULT CURRENTS; ERROR ANALYSIS; INTEGRATED CIRCUITS; OPTIMIZATION; PROBABILITY DENSITY FUNCTION; STATISTICAL METHODS;

EID: 3543057684     PISSN: 10637397     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1021813903727     Document Type: Article
Times cited : (15)

References (31)
  • 1
    • 84938162176 scopus 로고
    • Cost-size optima of monolithic integrated circuits
    • Murphy, B.T., Cost-Size Optima of Monolithic Integrated Circuits, Proc. IEEE, 1964, vol. 52, no. 12, pp. 1537-1545.
    • (1964) Proc. IEEE , vol.52 , Issue.12 , pp. 1537-1545
    • Murphy, B.T.1
  • 2
    • 0005900785 scopus 로고    scopus 로고
    • Yield, economic, and logistic models for complex digital arrays
    • Seeds, R.B., Yield, Economic, and Logistic Models for Complex Digital Arrays, in 7967 IEEE Int. Conv. Rec., part 6, pp. 61-66.
    • 7967 IEEE Int. Conv. Rec., Part 6 , pp. 61-66
    • Seeds, R.B.1
  • 3
    • 0015423592 scopus 로고
    • Analysis of yield of integrated circuits and a new expression for the yield
    • Okabe, T., Nagata, M., and Shimada, S., Analysis of Yield of Integrated Circuits and a New Expression for the Yield, Electr. Eng. Jpn., 1972, vol. 92, Dec., pp. 135-141.
    • (1972) Electr. Eng. Jpn. , vol.92 , Issue.DEC. , pp. 135-141
    • Okabe, T.1    Nagata, M.2    Shimada, S.3
  • 4
    • 0010968585 scopus 로고
    • Defect density distribution for LSI yield calculations
    • Stapper, C.H., Defect Density Distribution for LSI Yield Calculations, IEEE Trans. Electron Devices, 1973, vol. 20, no. 7, pp. 655-657.
    • (1973) IEEE Trans. Electron Devices , vol.20 , Issue.7 , pp. 655-657
    • Stapper, C.H.1
  • 5
    • 0004744726 scopus 로고
    • LSI yield modeling and process monitoring
    • Stapper, C.H., LSI Yield Modeling and Process Monitoring, IBM J. Res. Dev., 1976, vol. 20, no. 3, pp. 228-234.
    • (1976) IBM J. Res. Dev. , vol.20 , Issue.3 , pp. 228-234
    • Stapper, C.H.1
  • 6
    • 0020735104 scopus 로고
    • Integrated circuit yield statistics
    • Stapper, C.H., Armstrong, F.M., and Saji, K., Integrated Circuit Yield Statistics, Proc. IEEE, 1983, vol. 71, no. 4, pp. 453-470.
    • (1983) Proc. IEEE , vol.71 , Issue.4 , pp. 453-470
    • Stapper, C.H.1    Armstrong, F.M.2    Saji, K.3
  • 7
    • 0025433611 scopus 로고
    • The use and evaluation of yield models in integrated circuit manufacturing
    • Cunningham, J.A., The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing, IEEE Trans. Semicond. Manuf., 1990, vol. 3, no. 2, pp. 60-71.
    • (1990) IEEE Trans. Semicond. Manuf. , vol.3 , Issue.2 , pp. 60-71
    • Cunningham, J.A.1
  • 8
    • 0026128879 scopus 로고
    • Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement
    • Stapper, C.H., Statistics Associated with Spatial Fault Simulation Used for Evaluating Integrated Circuit Yield Enhancement, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 1991, vol. 10, no. 3, pp. 399-406.
    • (1991) IEEE Trans. Comput.-aided Des. Integr. Circuits Syst. , vol.10 , Issue.3 , pp. 399-406
    • Stapper, C.H.1
  • 9
    • 0029304862 scopus 로고
    • Integrated circuit yield management and yield analysis: Development and implementation
    • Stapper, C.H. and Rosner, R.J., Integrated Circuit Yield Management and Yield Analysis: Development and Implementation, IEEE Trans. Semicond. Manuf., 1995, vol. 8, pp. 95-102.
    • (1995) IEEE Trans. Semicond. Manuf. , vol.8 , pp. 95-102
    • Stapper, C.H.1    Rosner, R.J.2
  • 10
    • 0032628982 scopus 로고    scopus 로고
    • An overview of manufacturing yield and reliability modeling for semiconductor products
    • Kuo, W. and Kim, T., An Overview of Manufacturing Yield and Reliability Modeling for Semiconductor Products, Proc. IEEE, 1999, vol. 87, no. 8, pp. 1329-1345.
    • (1999) Proc. IEEE , vol.87 , Issue.8 , pp. 1329-1345
    • Kuo, W.1    Kim, T.2
  • 12
    • 0025457747 scopus 로고
    • Fault tolerance in VLSI circuits
    • Koren, I. and Singh, A.D., Fault Tolerance in VLSI Circuits, Computer, 1990, vol. 23, no. 7, pp. 73-83.
    • (1990) Computer , vol.23 , Issue.7 , pp. 73-83
    • Koren, I.1    Singh, A.D.2
  • 13
    • 0032164444 scopus 로고    scopus 로고
    • Defect tolerance in VLSI circuits: Techniques and yield analysis
    • Koren, I. and Koren, Z., Defect Tolerance in VLSI Circuits: Techniques and Yield Analysis, Proc. IEEE, 1998, vol. 86, no. 9, pp. 1819-1836.
    • (1998) Proc. IEEE , vol.86 , Issue.9 , pp. 1819-1836
    • Koren, I.1    Koren, Z.2
  • 15
    • 0034205833 scopus 로고    scopus 로고
    • Incorporating yield enhancement into the floorplanning process
    • Koren, I. and Koren, Z., Incorporating Yield Enhancement into the Floorplanning Process, IEEE Trans. Comput., 2000, vol. 49, no, 6, pp. 532-541.
    • (2000) IEEE Trans. Comput. , vol.49 , Issue.6 , pp. 532-541
    • Koren, I.1    Koren, Z.2
  • 17
    • 3543102865 scopus 로고    scopus 로고
    • Yield: Statistical modeling and enhancement techniques
    • Koren, I., Yield: Statistical Modeling and Enhancement Techniques, Yield Optimization and Test (YOT'01) Workshop, 2001, http://www.ecs.umass.edu/ece/ koren/yield/.
    • (2001) Yield Optimization and Test (YOT'01) Workshop
    • Koren, I.1
  • 24
    • 0024627901 scopus 로고
    • Small-area fault clusters and fault-tolerance in VLSI circuits
    • Stapper, C.H., Small-Area Fault Clusters and Fault-Tolerance in VLSI Circuits, IBM J. Res. Dev., 1989, vol. 33, pp. 174-177.
    • (1989) IBM J. Res. Dev. , vol.33 , pp. 174-177
    • Stapper, C.H.1
  • 25
    • 0027607627 scopus 로고
    • A unified negative-binomial distribution for yield analysis of defect-tolerant circuits
    • Koren, I., Koren, Z., and Stapper, C.H., A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits, IEEE Trans. Comput., 1993, vol. 42, no. 6, pp. 724-734.
    • (1993) IEEE Trans. Comput. , vol.42 , Issue.6 , pp. 724-734
    • Koren, I.1    Koren, Z.2    Stapper, C.H.3
  • 28
    • 0010719556 scopus 로고
    • Translated under the title, Moscow: Mir
    • Feller, W., An Introduction to Probability Theory and Its Applications, 2 vols., New York: Wiley, 1970, 3rd ed. Translated under the title Vvedenie v teoriyu veroyatnostei i ee prilozheniya, Moscow: Mir, 1984.
    • (1984) Vvedenie v Teoriyu Veroyatnostei i ee Prilozheniya
  • 31
    • 0039802058 scopus 로고
    • Analysis of variations and control-chart definition in microelectronics
    • Bogdanov, Yu.I., Analysis of Variations and Control-Chart Definition in Microelectronics, Mikroelektronika, 1995, vol. 24, no. 6, pp. 435-446.
    • (1995) Mikroelektronika , vol.24 , Issue.6 , pp. 435-446
    • Bogdanov, Yu.I.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.