Determination of yield bounds prior to routing

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1999, Pages 4-13

  Venkataraman, Arunshankar ^a   Koren, Israel ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN;

VANILLA ROUTING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033334557     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)