Software decelerators

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2778, Issue , 2003, Pages 385-395

  Keller, Eric ^a   Brebner, Gordon ^a   James Roxby, Phil ^a  

^a XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC CIRCUITS;

EFFICIENT DESIGNS; EMBEDDED PROCESSORS; FINITE STATE MACHINE MODEL; LOGIC RESOURCES; LOGIC-CENTRIC SYSTEMS; LOWER-POWER CONSUMPTION; TECHNOLOGY INDEPENDENT DESIGN; TIMING PERFORMANCE;

INTEGRATED CIRCUIT DESIGN;

EID: 35248819762     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-45234-8_38     Document Type: Article

References (6)

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2. Gordon Brebner. Single-chip Gigabit mixed-version IP router on Virtex-II Pro. IEEE Symposium on FPGAs for Custom Computing Machines (FCCM02), pp.35-44, April 2002.
3. M. Dales. The Proteus processor - a conventional CPU with reconfigurable functionality. 9th Int. Workshop on Field Programmable Logic (FPL99), pp.431-437, September 1999.
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5. M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiovanni-Vincentelli. Addressing the system-on-a-chip interconnect woes through communication-based design. ACM/IEEE Design Automation Conference (DAC01), pp.667-672, June 2001.
6. S. Singh and R. Slous. Accelerating Adobe Photoshop with reconfigurable logic. IEEE Symposium on FPGAs for Custom Computing Machines (FCCM98), pp. 15-17, April 1998.