Single-chip gigabit mixed-version IP Router on Virtex-II Pro

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2002-January, Issue , 2002, Pages 35-44

  Brebner, Gordon ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

BASE STATIONS; BROADBAND NETWORKS; CARRY LOGIC; COMPUTATION THEORY; COMPUTER ARCHITECTURE; COMPUTERS; ETHERNET; INTERNET PROTOCOLS; TELECOMMUNICATION NETWORKS;

ETHERNET PORTS; GIGABIT ETHERNET; INCOMING PACKETS; IP ROUTERS; MASTER SLAVE; MULTI-THREADING; REAL PART; SINGLE CHIPS;

ROUTERS;

EID: 84950121818     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2002.1106659     Document Type: Conference Paper

References (12)

1. Braun F, J Lockwood and M Waldvogel, "Reconfigurable router modules using network protocol wrappers", Proc. 11th International Conference on Field-Programmable Logic and Applications, Springer LNCS 2147, 2001, pp. 254-263.
2. Brebner G and A Donlin, "Runtime reconfigurable routing", Proc. 5th Reconfigurable Architecture Workshop, Springer LNCS 1388, 1998, pp. 25-30.
3. Brebner G, "Highly reconfigurable communication protocol multiplexing element for SCOPH", Reconfigurable Technology, Proceedings of SPIE, 4525, 2001, pp. 99-106.
4. Comer D, Chapter 22 of "Computer Networks and Internets" (3rd ed.), Prentice-Hall, 2001.
5. Ditmar J, K Torkelsson and A Jantsch, "A dynamically reconfigurable FPGA-based content addressable memory for Internet protocol characterization", Proc. 10th International Conference on Field-Programmable Logic and Applications, Springer LNCS 1896, 2000, pp. 19-28.
6. Dollas A et al, "Architecture and applications of PLATO:...", Proc. 9th IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Press, 2001.
7. Fallside H and M Smith, "Internet connected FPL", Proc. 10th International Conference on Field-Programmable Logic and Applications, Springer LNCS 1896, 2000, pp. 48-57.
8. Guccione S, D Levi and D Downs, A reconfigurable content addressable memory", Proc. 7th Reconfigurable Architecture Workshop, Springer LNCS 1800, 2000, pp. 882-889.
9. Hinden R, S Deering and M O'Dell, "An aggregatable global unicast address format", Internet Request for Comments RFC2374, 1998.
10. Lockwood J, N Naufel, J Turner and D Taylor, "Reprogrammable network packet processing on the Field Programmable Extender (FPX) ", Proc. 9th International Symposium on Field Programmable Gate Arrays, ACM Press, 2001, pp. 87-93.
11. http://www.6bone.net
12. http://www.xilinx.com/products/platform