The proteus processor-a conventional CPU with reconfigurable functionality

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1673, Issue , 1999, Pages 431-437

  Dales, Michael ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY;

BACKGROUND INFORMATION; COMPUTING SCIENCE; PERFORMANCE GAIN; RECONFIGURABLE; RECONFIGURABLE LOGIC; RUNNING APPLICATIONS; S FUNCTION; UNIVERSITY OF GLASGOW;

RECONFIGURABLE HARDWARE;

EID: 84956861525     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-48302-1_49     Document Type: Conference Paper

References (14)

1. M. Abrash. Ramblings In Real Time. Dr. Dobbs Source Book, November/December 1996.
2. J. Burns, A. Donlin, J. Hogg, S. Singh, and M. deWit. ADynamic Reconfiguration Run-Time System. In IEEE Workshop on FPGAs for Custom Computing Machines, April 1997.
3. Cyrix Corporation. Cyrix MediaGX Processor Frequently Asked Questions, January 1999.
4. th International Workshop on Field Programmable Logic and Applications, September 1998.
5. E.E. Times. Intel preps plan to bust bugs in Pentium MPUs, June 1997. 30th June.
6. R. W. Hartenstein, K. Schmidt, H. Reinig, and M. Weber. A Novel Compilation Technique for a Machine Paradigm Based on Field-Programmable Logic. In International Workshop on Field Programmable Logic and Applications, September 1991.
7. J. R. Hauser and J. Wawrzynek. Garp: A MIPS Processor with a Reconfigurable Coprocessor. In IEEE Workshop on FPGAs for Custom Computing Machines, September 1997.
8. Intel Corporation. Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture. Intel Corporation, January 1998.
9. S. Sawitzki, A. Gratz, and R. G. Spallek. CoMPARE: A Simple Reconfigurable Processor Architecture Exploiting Instruction Level Parallelism. In Proceedings of the 5th Australasian Conference on Parallel and Real-Time Systems, 1998.
10. th International Workshop on Field Programmable Logic and Applications, September 1997.
11. C. Small and M. Seltzer. A Comparison of OS Extension Technologies. In Proceedings of the USENIX 1996 annual technical conference, January 1996.
12. Triscend Corporation. Triscend corporation web page, January 1999
13. M. J. Wirthlin and B. L. Hutchings. A Dynamic Instruction Set Computer. In IEEEWorkshop on FPGAs for Custom Computing Machines, April 1995
14. M. J. Wirthlin, B. L. Hutchins, and K. L. Gilson. The Nano Processor: a Low Resource Reconfigurable Processor. In IEEE Workshop on FPGAs for Custom Computing Machines, April 1994