Improving the security of dual-rail circuits

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3156, Issue , 2004, Pages 282-297

  Sokolov, Danil ^a   Murphy, Julian ^a   Bystrov, Alex ^a   Yakovlev, Alex ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; COMPUTER AIDED DESIGN; CRYPTOGRAPHY; DATA PRIVACY; EMBEDDED SYSTEMS; RECONFIGURABLE HARDWARE; SIDE CHANNEL ATTACK;

ADVANCED ENCRYPTION STANDARD; AUTOMATED TOOLS; CLOCK CYCLES; DIFFERENTIAL POWER ANALYSIS ATTACK; DUAL RAIL CIRCUIT; DUAL RAIL ENCODING; DUAL-RAIL LOGIC; RISE-TO-POWER;

COMPUTER CIRCUITS;

EID: 35048904617     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-28632-5_21     Document Type: Article

References (16)

1. H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, S. Kim, W. Zhang: "Masking the energy behaviour of DES Encryption". Proc. DATE'03, Munich, Germany, March 2003.
2. K. Tiri, M. Akmal, I. Verbauwhede: "A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards". Proc. ESSCIRC 2002.
3. S. Moore, R. Anderson, P. Cunningham, R. Mullins, G. Taylor: "Improving smart card security using self-timed circuits". ASYNC'02, 2002, pp. 211-218.
4. Z. Yu, S. Furber, L. Plana: "An investigation into the security of self-timed circuits". Proc. of ASYNC'03, Vancouver, May 2003, IEEE CS Press, pp. 206-215.
5. A. Kondratyev, K. Lwin: "Design of asynchronous circuits using synchronous CAD tools". Proc. DAC'02, New Orleans, USA, 2002, pp. 107-117.
6. V. Varshavsky (editor): "Self-timed control of concurrent processes" Kluwer, 1990 (Russian edition 1986).
7. I. David, R. Ginosar, M. Yoeli: "An efficient implementation of boolean functions as self-timed circuits". IEEE Trans, on Computers, 1992, 41(1), pp. 2-11.
8. K. Fant, S. Brandt: "Null Convention Logic: a complete and consistent logic for asynchronous digital circuit synthesis". Proc. Int. Conf. Application-Specific Systems, Architectures and Processors (ASAP'96), IEEE CS Press, Los Alamos, Calif. , 1996, pp. 261-273.
9. A. Bystrov, D. Sokolov, A. Yakovlev, A. Koelmans: "Balancing Power Signature in Secure Systems". 14th UK Asynchronous Forum, Newcastle, June 2003.
10. D. Sokolov, J. Murphy, A. Bystrov, A. Yakovlev: "Improving the security of dual-rail circuits", Technical report, Microelectronic System Design Group, School of EECE, University of Newcastle upon Tyne, April 2004, http://www. staff. ncl. ac. uk/i. g. clark/async/tech-reports/NCLEECE-MSD-TR- 2004-101. pdf
11. W. Bainbridge, S. Furber: "Delay insensitive system-on-chip interconnect using l-of-4 data encoding". In Proc. ASYNC'01, March 2001.
12. S. Mangard, M. Aigner, S. Dominikus: "A Highly Regular and Scalable AES Hardware Architecture". IEEE Trans. On Computers, 2003, 52(4), pp. 483-491
13. J. Daemen, V. Rijmen: "The Design of Rijndael". Springer-Verlag, 2002
14. National Institute Of Standards and Technology: "Federal Information Processing Standard 197, The Advanced Encryption Standard (AES)". http://csrc. nist. gov/publications/fips/fips197/fips197. pdf, 2001.
15. R. Usselmann: "Advanced Encryption Standard / Rijndael IP Core", http://www. asic. ws/.
16. J. Wolkerstorfer, E. Oswald, M. Lamberger: "An ASIC implementation of AES S-Boxes", Topics in Cryptology RSA'02, Proc. RSA Conf. 2002, Feb 2002.