Code generation for a dual instruction set processor based on selective code transformation

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2826, Issue , 2003, Pages 33-48

  Lee, Sheayun ^a   Lee, Jaejin ^a   Min, Sang Lyul ^a   Hiser, Jason ^b   Davidson, Jack W ^b  

^a Seoul National University   (South Korea)

^b University of Virginia   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; COSINE TRANSFORMS; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; SIZE DETERMINATION;

CODE TRANSFORMATION; COST-SENSITIVE EMBEDDED SYSTEMS; DEGRADED PERFORMANCE; EFFECTIVE MECHANISMS; INSTRUCTION SET PROCESSORS; PROFITABILITY ANALYSIS; REDUCED INSTRUCTION SETS; TRADE-OFF RELATIONSHIP;

CODES (SYMBOLS);

EID: 33745877781     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-39920-9_4     Document Type: Article

References (16)

1. A. Halambi, A. Shrivastava, P. Biswas, N. Dutt, and A. Nicolau. An efficient compiler technique for code size reduction using reduced bit-width ISAs. In Proceedings of the DATE (Design, Automation and Test in Europe), Paris, France, March 2002.
2. S. Furber. ARM System Architecture. Addison-Wesley, 1996. ISBN 0-201-40352-8.
3. K. Kissel. MIPS16: High-density MIPS for the embedded market. Technical report, Silicon Graphics MIPS Group, 1997.
4. ARC Cores (http://www.arc.com). The ARCtangent-A5 Processor.
5. A. Appel, J. Davidson, and N. Ramsey. The zephyr compiler infrastructure, http://www.cs.virginia.edu/zephyr, 1998.
6. A. Krishnaswamy and R. Gupta. Profile guided selection of ARM and Thumb instructions. In Proceedings of LCTES/SCOPES, Berlin, Germany, June 2002.
7. L. Goudge and S. Segars. Thumb: Reducing the cost of 32-bit RISC performance in portable and consumer applications. In Proceedings of COMPCON, 1996.
8. ARM Limited. ARM Developer Suite Developer Guide.
9. T. Ball and J.R. Larus. Efficient path profiling. In Proceedings of the 29th Annual IEEE/ACM Symposium on Microarchitecture, pages 46-57, Paris, France, 1996.
10. M.E. Benitez and J.W. Davidson. Target-specific global code improvement: Principles and applications. Technical Report CS-94-42, Department of Computer Science, University of Virginia, April 1994.
11. J.W. Davidson and C.W. Fraser. Code selection through object code optimization. ACM Transactions on Programming Languages and Systems, 6(4):505-526, October 1984.
12. J.W. Davidson and D.B. Whalley. A design environment for addressing architecture and compiler interactions. Microprocessors and Microsystems, 15(9):459-472, November 1991.
13. A. Tamches and B.P. Miller. Dynamic kernel code optimization. In Proceedings of the 3rd Workshop on Binary Translation, Barcelona, Spain, June 2001.
14. M.R. Guthaus, J.S. Ringenberg, D. Ernst, T.M. Austin, T. Mudge, and R.B. Brown. MiBench: A free, commercially representative embedded benchmark suite. In Proceedings of the IEEE 4th Annual Workshop on Workload Characterization, Austin, TX, December 2001.
15. C. Lee, M. Potkonjak, and W.H. Mangione-Smith. MediaBench: A tool for evaluating and synthesizing multimedia and communications systems. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 330-335, December 1997.
16. ARM Linux Project. http://www.arm.linux.org.uk.