A worst case timing analysis technique for optimized programs

Proceedings - 5th International Conference on Real-Time Computing Systems and Applications, RTCSA 1998

Volumn 1998-October, Issue , 1998, Pages 151-157

  Lim, Sung Soo ^a   Kim, Jihong ^a   Min, Sang Lyul ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; HIGH LEVEL LANGUAGES; REAL TIME SYSTEMS; TIMING CIRCUITS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

COMPILER-ASSISTED; CONTROL STRUCTURE; HIERARCHICAL REPRESENTATION; HIERARCHICAL TIMING ANALYSIS; HIGH-LEVEL PROGRAMMING LANGUAGE; OPTIMIZING COMPILERS; PROOF OF CONCEPT; WORST-CASE EXECUTION TIME;

PROGRAM COMPILERS;

EID: 84930463266     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTCSA.1998.726411     Document Type: Conference Paper

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