VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization

2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Volumn , Issue , 2007, Pages 89-92

  Song, Yang ^a   Liu, Zhenyu ^a   Ikenaga, Takeshi ^a   Goto, Satoshi ^a  

^a WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

SCHEDULING; STATIC RANDOM ACCESS STORAGE; VLSI CIRCUITS;

CLOCK FREQUENCY; SUM OF ABSOLUTE DIFFERENCES (SAD); VARIABLE BLOCK SIZES MOTION ESTIMATION (VBSME);

MOTION ESTIMATION;

EID: 34748921005     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2006.258131     Document Type: Conference Paper

References (7)

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2. "Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T Rec. H.264 ISO/IEC 14496-10 AVC)", 2003.
3. Y. W. Huang, T. C. Wang, B. Y. Hsieh, L. G. Chen, "Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264", IEEE ISCAS'03 Vol. 2, pp. 796-799, 2003.
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7. P. Kuhn, Algorithms, complexity analysis: and VLSI architectures for MPEG-4 motion estimation, Kluwer Academic Publishers, pp. 134-148, 1999.