Assessing the effect of die sealing in Cu/low-k structures

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

Volumn , Issue , 2007, Pages 138-140

  Kearney, Andrew V ^a   Vairagar, Anand V ^b   Geisler, Holm ^b   Zschech, Ehrenfried ^b   Dauskardt, Reinhold H ^a  

^a Stanford University   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CYCLIC LOADS; DIELECTRIC DEVICES; FRACTURE MECHANICS; MICROELECTRONICS; POROUS MATERIALS; SILICON WAFERS;

CYCLIC FATIGUE LOADING; DIE SEALING; INTERCONNECT STRUCTURE;

SEALING (CLOSING);

SEALING; SILICON;

EID: 34748886283     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iitc.2007.382363     Document Type: Conference Paper

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