MMIC compatible wafer-level packaging technology

Conference Proceedings - International Conference on Indium Phosphide and Related Materials

Volumn , Issue , 2007, Pages 14-17

  Chang Chien, P ^a   Zeng, X ^a   Tornquist, K ^a   Nishimoto, M ^a   Battung, M ^a   Chung, Y ^a   Yang, J ^a   Farkas, D ^a   Yajima, M ^a   Cheung, C ^a   Luo, K ^a   Eaves, D ^a   Lee, J ^a   Uyeda, J ^a   Duan, D ^a   Fordham, O ^a   Chung, T ^a   Sandhu, R ^a   Tsai, R ^a  

^a NORTHROP GRUMMAN CORPORATION   (United States)

Author keywords

Bonding; Heterogeneous integration; MMIC packaging; Wafer scale assembly; Wafer level packaging

Indexed keywords

CHIP SCALE PACKAGES; COST EFFECTIVENESS; DIGITAL INTEGRATED CIRCUITS; MILITARY APPLICATIONS; THREE DIMENSIONAL;

HETEROGENEOUS INTEGRATION; NORTHROP GRUMMAN SPACE TECHNOLOGY (NGST) (CO); WAFER SCALE ASSEMBLY;

MONOLITHIC MICROWAVE INTEGRATED CIRCUITS;

EID: 34748877675     PISSN: 10928669     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICIPRM.2007.380677     Document Type: Conference Paper

References (8)

1. P. Chang-Chien, et al. "Low temperature, hermetic, high-yield wafer-level packaging technology", Northrop Grumman Technology Review Journal, spring/summer 2006, vol. 14, number 1, pp. 77-97.
2. th meeting of the electrochemical Society, May 2005, Quebec City, Canada, pp. 301-313.
3. P. Chang-Chien, et al. "Multi-Layer MMIC Integration Using Wafer-Scale Assembly". Government microcircuit application conference (GOMAC), March 2007, Lake Buena Vista, FL.
4. th meeting of the electrochemical society, May 2007, Chicago, IL. Paper E5-03500.
5. P. Chang-Chien, et al. "Dense Intra-Cavity Interconnection Technology for Hermetically packaged MMICs" Symposium "State-of-the-Art Program on Compound Semiconductors 45", SOTAPOCS 45) Oct. 2006, Cancun, Mexico, paper number 1532.
6. M. Yajima, et al. "High Yield Intra-Cavity Interconnection Fabrication Method and Characterization Methodologies" 2007 International Conference on Compound Semiconductor Manufacturing Technology (CSMANTECH), May 2007, Austin TX, paper 8.3.
7. D. Farkas, et al. "Demonstration of a Low Loss W-Band Interconnect and Circuit Isolation Structure for Wafer Scale Assembly" IEEE MTT-S International Mcirowave Symposium, IMS 2007, Honolulu, Haiwaii, June 2007.
8. J. Yang et al. "Wafer level integrated antenna front end module for low cost phased array implementation" IEEE MTT-S International Mcirowave Symposium, IMS 2007, Honolulu, Haiwaii, June 2007.